Commit 56c9d1a0 authored by Marek Vasut's avatar Marek Vasut Committed by Linus Walleij
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dt-bindings: pinctrl: fsl,imx6ul-pinctrl: Convert i.MX35/5x/6 to YAML



The IOMUXC controller description is almost identical on i.MX35/5x/6 SoCs,
except for the configuration bits which differ across SoCs. Rename the
fsl,imx6ul-pinctrl.yaml to fsl,imx35-pinctrl.yaml, fill in compatible
strings for the other SoCs and fill in the various bits into desciption.
This way, i.MX35/5x/6 series SoCs can all be converted to DT schema.
Remove the old text DT bindings description.

Reviewed-by: default avatarRob Herring (Arm) <robh@kernel.org>
Signed-off-by: default avatarMarek Vasut <marex@denx.de>
Link: https://lore.kernel.org/20241017211241.170861-1-marex@denx.de


Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent b509b5e5
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* Freescale IMX35 IOMUX Controller

Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
and usage.

Required properties:
- compatible: "fsl,imx35-iomuxc"
- fsl,pins: two integers array, represents a group of pins mux and config
  setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
  pin working on a specific function, CONFIG is the pad setting value like
  pull-up for this pin. Please refer to imx35 datasheet for the valid pad
  config settings.

CONFIG bits definition:
PAD_CTL_DRIVE_VOLAGAGE_18	(1 << 13)
PAD_CTL_DRIVE_VOLAGAGE_33	(0 << 13)
PAD_CTL_HYS			(1 << 8)
PAD_CTL_PKE			(1 << 7)
PAD_CTL_PUE			(1 << 6)
PAD_CTL_PUS_100K_DOWN		(0 << 4)
PAD_CTL_PUS_47K_UP		(1 << 4)
PAD_CTL_PUS_100K_UP		(2 << 4)
PAD_CTL_PUS_22K_UP		(3 << 4)
PAD_CTL_ODE_CMOS		(0 << 3)
PAD_CTL_ODE_OPENDRAIN		(1 << 3)
PAD_CTL_DSE_NOMINAL		(0 << 1)
PAD_CTL_DSE_HIGH		(1 << 1)
PAD_CTL_DSE_MAX			(2 << 1)
PAD_CTL_SRE_FAST		(1 << 0)
PAD_CTL_SRE_SLOW		(0 << 0)

Refer to imx35-pinfunc.h in device tree source folder for all available
imx35 PIN_FUNC_ID.
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/fsl,imx6ul-pinctrl.yaml#
$id: http://devicetree.org/schemas/pinctrl/fsl,imx35-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale IMX6UL IOMUX Controller
title: Freescale IMX35/IMX5x/IMX6 IOMUX Controller

maintainers:
  - Dong Aisheng <aisheng.dong@nxp.com>
@@ -18,9 +18,21 @@ allOf:

properties:
  compatible:
    enum:
    oneOf:
      - enum:
          - fsl,imx35-iomuxc
          - fsl,imx51-iomuxc
          - fsl,imx53-iomuxc
          - fsl,imx6dl-iomuxc
          - fsl,imx6q-iomuxc
          - fsl,imx6sl-iomuxc
          - fsl,imx6sll-iomuxc
          - fsl,imx6sx-iomuxc
          - fsl,imx6ul-iomuxc
          - fsl,imx6ull-iomuxc-snvs
      - items:
          - const: fsl,imx50-iomuxc
          - const: fsl,imx53-iomuxc

  reg:
    maxItems: 1
@@ -39,9 +51,9 @@ patternProperties:
          each entry consists of 6 integers and represents the mux and config
          setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
          mux_val input_val> are specified using a PIN_FUNC_ID macro, which can
          be found in <arch/arm/boot/dts/imx6ul-pinfunc.h>. The last integer
          be found in <arch/arm/boot/dts/nxp/imx/imx*-pinfunc.h>. The last integer
          CONFIG is the pad setting value like pull-up on this pin. Please
          refer to i.MX6UL Reference Manual for detailed CONFIG settings.
          refer to matching i.MX Reference Manual for detailed CONFIG settings.
        $ref: /schemas/types.yaml#/definitions/uint32-matrix
        items:
          items:
@@ -56,7 +68,41 @@ patternProperties:
            - description: |
                "input_val" indicates the select input value to be applied.
            - description: |
                "pad_setting" indicates the pad configuration value to be applied:
                "pad_setting" indicates the pad configuration value to be applied.
                Common i.MX35
                  PAD_CTL_DRIVE_VOLAGAGE_18       (1 << 13)
                  PAD_CTL_DRIVE_VOLAGAGE_33       (0 << 13)
                  PAD_CTL_HYS                     (1 << 8)
                  PAD_CTL_PKE                     (1 << 7)
                  PAD_CTL_PUE                     (1 << 6)
                  PAD_CTL_PUS_100K_DOWN           (0 << 4)
                  PAD_CTL_PUS_47K_UP              (1 << 4)
                  PAD_CTL_PUS_100K_UP             (2 << 4)
                  PAD_CTL_PUS_22K_UP              (3 << 4)
                  PAD_CTL_ODE_CMOS                (0 << 3)
                  PAD_CTL_ODE_OPENDRAIN           (1 << 3)
                  PAD_CTL_DSE_NOMINAL             (0 << 1)
                  PAD_CTL_DSE_HIGH                (1 << 1)
                  PAD_CTL_DSE_MAX                 (2 << 1)
                  PAD_CTL_SRE_FAST                (1 << 0)
                  PAD_CTL_SRE_SLOW                (0 << 0)
                Common i.MX50/i.MX51/i.MX53 bits
                  PAD_CTL_HVE                     (1 << 13)
                  PAD_CTL_HYS                     (1 << 8)
                  PAD_CTL_PKE                     (1 << 7)
                  PAD_CTL_PUE                     (1 << 6)
                  PAD_CTL_PUS_100K_DOWN           (0 << 4)
                  PAD_CTL_PUS_47K_UP              (1 << 4)
                  PAD_CTL_PUS_100K_UP             (2 << 4)
                  PAD_CTL_PUS_22K_UP              (3 << 4)
                  PAD_CTL_ODE                     (1 << 3)
                  PAD_CTL_DSE_LOW                 (0 << 1)
                  PAD_CTL_DSE_MED                 (1 << 1)
                  PAD_CTL_DSE_HIGH                (2 << 1)
                  PAD_CTL_DSE_MAX                 (3 << 1)
                  PAD_CTL_SRE_FAST                (1 << 0)
                  PAD_CTL_SRE_SLOW                (0 << 0)
                Common i.MX6 bits
                  PAD_CTL_HYS                     (1 << 16)
                  PAD_CTL_PUS_100K_DOWN           (0 << 14)
                  PAD_CTL_PUS_47K_UP              (1 << 14)
@@ -69,6 +115,11 @@ patternProperties:
                  PAD_CTL_SPEED_MED               (1 << 6)
                  PAD_CTL_SPEED_HIGH              (3 << 6)
                  PAD_CTL_DSE_DISABLE             (0 << 3)
                  PAD_CTL_SRE_FAST                (1 << 0)
                  PAD_CTL_SRE_SLOW                (0 << 0)
                i.MX6SL/MX6SLL specific bits
                  PAD_CTL_LVE                     (1 << 22) (MX6SL/SLL only)
                i.MX6SLL/i.MX6SX/i.MX6UL/i.MX6ULL specific bits
                  PAD_CTL_DSE_260ohm              (1 << 3)
                  PAD_CTL_DSE_130ohm              (2 << 3)
                  PAD_CTL_DSE_87ohm               (3 << 3)
@@ -76,8 +127,14 @@ patternProperties:
                  PAD_CTL_DSE_52ohm               (5 << 3)
                  PAD_CTL_DSE_43ohm               (6 << 3)
                  PAD_CTL_DSE_37ohm               (7 << 3)
                  PAD_CTL_SRE_FAST                (1 << 0)
                  PAD_CTL_SRE_SLOW                (0 << 0)
                i.MX6DL/i.MX6Q/i.MX6SL specific bits
                  PAD_CTL_DSE_240ohm              (1 << 3)
                  PAD_CTL_DSE_120ohm              (2 << 3)
                  PAD_CTL_DSE_80ohm               (3 << 3)
                  PAD_CTL_DSE_60ohm               (4 << 3)
                  PAD_CTL_DSE_48ohm               (5 << 3)
                  PAD_CTL_DSE_40ohm               (6 << 3)
                  PAD_CTL_DSE_34ohm               (7 << 3)

    required:
      - fsl,pins
@@ -114,3 +171,14 @@ examples:
        >;
      };
    };
  - |
    iomuxc_mx6q: pinctrl@20e0000 {
        compatible = "fsl,imx6q-iomuxc";
        reg = <0x20e0000 0x4000>;

        pinctrl_uart4: uart4grp {
            fsl,pins =
                <0x288 0x658 0x000 0x3 0x0	0x140>,
                <0x28c 0x65c 0x938 0x3 0x3	0x140>;
        };
    };
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* Freescale IMX50 IOMUX Controller

Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
and usage.

Required properties:
- compatible: "fsl,imx50-iomuxc"
- fsl,pins: two integers array, represents a group of pins mux and config
  setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
  pin working on a specific function, CONFIG is the pad setting value like
  pull-up for this pin. Please refer to imx50 datasheet for the valid pad
  config settings.

CONFIG bits definition:
PAD_CTL_HVE			(1 << 13)
PAD_CTL_HYS			(1 << 8)
PAD_CTL_PKE			(1 << 7)
PAD_CTL_PUE			(1 << 6)
PAD_CTL_PUS_100K_DOWN		(0 << 4)
PAD_CTL_PUS_47K_UP		(1 << 4)
PAD_CTL_PUS_100K_UP		(2 << 4)
PAD_CTL_PUS_22K_UP		(3 << 4)
PAD_CTL_ODE			(1 << 3)
PAD_CTL_DSE_LOW			(0 << 1)
PAD_CTL_DSE_MED			(1 << 1)
PAD_CTL_DSE_HIGH		(2 << 1)
PAD_CTL_DSE_MAX			(3 << 1)
PAD_CTL_SRE_FAST		(1 << 0)
PAD_CTL_SRE_SLOW		(0 << 0)

Refer to imx50-pinfunc.h in device tree source folder for all available
imx50 PIN_FUNC_ID.
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* Freescale IMX51 IOMUX Controller

Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
and usage.

Required properties:
- compatible: "fsl,imx51-iomuxc"
- fsl,pins: two integers array, represents a group of pins mux and config
  setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
  pin working on a specific function, CONFIG is the pad setting value like
  pull-up for this pin. Please refer to imx51 datasheet for the valid pad
  config settings.

CONFIG bits definition:
PAD_CTL_HVE			(1 << 13)
PAD_CTL_HYS			(1 << 8)
PAD_CTL_PKE			(1 << 7)
PAD_CTL_PUE			(1 << 6)
PAD_CTL_PUS_100K_DOWN		(0 << 4)
PAD_CTL_PUS_47K_UP		(1 << 4)
PAD_CTL_PUS_100K_UP		(2 << 4)
PAD_CTL_PUS_22K_UP		(3 << 4)
PAD_CTL_ODE			(1 << 3)
PAD_CTL_DSE_LOW			(0 << 1)
PAD_CTL_DSE_MED			(1 << 1)
PAD_CTL_DSE_HIGH		(2 << 1)
PAD_CTL_DSE_MAX			(3 << 1)
PAD_CTL_SRE_FAST		(1 << 0)
PAD_CTL_SRE_SLOW		(0 << 0)

Refer to imx51-pinfunc.h in device tree source folder for all available
imx51 PIN_FUNC_ID.
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* Freescale IMX53 IOMUX Controller

Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
and usage.

Required properties:
- compatible: "fsl,imx53-iomuxc"
- fsl,pins: two integers array, represents a group of pins mux and config
  setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
  pin working on a specific function, CONFIG is the pad setting value like
  pull-up for this pin. Please refer to imx53 datasheet for the valid pad
  config settings.

CONFIG bits definition:
PAD_CTL_HVE			(1 << 13)
PAD_CTL_HYS			(1 << 8)
PAD_CTL_PKE			(1 << 7)
PAD_CTL_PUE			(1 << 6)
PAD_CTL_PUS_100K_DOWN		(0 << 4)
PAD_CTL_PUS_47K_UP		(1 << 4)
PAD_CTL_PUS_100K_UP		(2 << 4)
PAD_CTL_PUS_22K_UP		(3 << 4)
PAD_CTL_ODE			(1 << 3)
PAD_CTL_DSE_LOW			(0 << 1)
PAD_CTL_DSE_MED			(1 << 1)
PAD_CTL_DSE_HIGH		(2 << 1)
PAD_CTL_DSE_MAX			(3 << 1)
PAD_CTL_SRE_FAST		(1 << 0)
PAD_CTL_SRE_SLOW		(0 << 0)

Refer to imx53-pinfunc.h in device tree source folder for all available
imx53 PIN_FUNC_ID.
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