Commit 56cd8adf authored by Rob Clark's avatar Rob Clark
Browse files

drm/msm: Fix x2-85 TPL1_DBG_ECO_CNTL1 



We actually need to set b26, just claiming to do so is not enough :-)

Fixes: 01ff3bf2 ("drm/msm/a8xx: Add support for Adreno X2-85 GPU")
Signed-off-by: default avatarRob Clark <robin.clark@oss.qualcomm.com>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/697778/
Message-ID: <20260109153730.130462-2-robin.clark@oss.qualcomm.com>
parent dcbd2f82

drivers/gpu/drm/msm/adreno/a6xx_catalog.c

+1 −1
Original line number Diff line number Diff line
@@ -1689,7 +1689,7 @@ static const struct adreno_reglist_pipe x285_nonctxt_regs[] = { 
	{ REG_A7XX_SP_READ_SEL, 0x0001ff00, BIT(PIPE_NONE) },

	{ REG_A6XX_TPL1_DBG_ECO_CNTL, 0x10000000, BIT(PIPE_NONE) },

	/* BIT(26): Disable final clamp for bicubic filtering */

	{ REG_A6XX_TPL1_DBG_ECO_CNTL1, 0x00000720, BIT(PIPE_NONE) },

	{ REG_A6XX_TPL1_DBG_ECO_CNTL1, 0x04000720, BIT(PIPE_NONE) },

	{ REG_A6XX_UCHE_MODE_CNTL, 0x80080000, BIT(PIPE_NONE) },

	{ REG_A8XX_UCHE_CCHE_MODE_CNTL, 0x00001000, BIT(PIPE_NONE) },

	{ REG_A8XX_UCHE_CCHE_CACHE_WAYS, 0x00000800, BIT(PIPE_NONE) },