Commit 56e54601 authored by Michal Simek's avatar Michal Simek
Browse files

arm64: zynqmp: Wire qspi on multiple boards 



Couple of boards have qspi on the board that's why enable controller and
describe them.

Signed-off-by: default avatarMichal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/01a69ee6590245b5bee70a2553f6faac0d31ca76.1623684253.git.michal.simek@xilinx.com
parent f4be206c

arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts

+15 −1
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ 
/*

 * dts file for Xilinx ZynqMP ZC1232

 *

 * (C) Copyright 2017 - 2019, Xilinx, Inc.

 * (C) Copyright 2017 - 2021, Xilinx, Inc.

 *

 * Michal Simek <michal.simek@xilinx.com>

 */
@@ -19,6 +19,7 @@ / { 
	aliases {

		serial0 = &uart0;

		serial1 = &dcc;

		spi0 = &qspi;

	};



	chosen {
@@ -36,6 +37,19 @@ &dcc { 
	status = "okay";

};



&qspi {

	status = "okay";

	flash@0 {

		compatible = "m25p80", "jedec,spi-nor"; /* 32MB */

		#address-cells = <1>;

		#size-cells = <1>;

		reg = <0x0>;

		spi-tx-bus-width = <1>;

		spi-rx-bus-width = <4>;

		spi-max-frequency = <108000000>; /* Based on DC1 spec */

	};

};



&sata {

	status = "okay";

	/* SATA OOB timing settings */

arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts

+15 −1
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ 
/*

 * dts file for Xilinx ZynqMP ZC1254

 *

 * (C) Copyright 2015 - 2019, Xilinx, Inc.

 * (C) Copyright 2015 - 2021, Xilinx, Inc.

 *

 * Michal Simek <michal.simek@xilinx.com>

 * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
@@ -20,6 +20,7 @@ / { 
	aliases {

		serial0 = &uart0;

		serial1 = &dcc;

		spi0 = &qspi;

	};



	chosen {
@@ -37,6 +38,19 @@ &dcc { 
	status = "okay";

};



&qspi {

	status = "okay";

	flash@0 {

		compatible = "m25p80", "jedec,spi-nor"; /* 32MB */

		#address-cells = <1>;

		#size-cells = <1>;

		reg = <0x0>;

		spi-tx-bus-width = <1>;

		spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */

		spi-max-frequency = <108000000>; /* Based on DC1 spec */

	};

};



&uart0 {

	status = "okay";

};

arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts

+14 −0
Original line number Diff line number Diff line
@@ -26,6 +26,7 @@ aliases { 
		mmc1 = &sdhci1;

		rtc0 = &rtc;

		serial0 = &uart0;

		spi0 = &qspi;

	};



	chosen {
@@ -339,6 +340,19 @@ conf { 
	};

};



&qspi {

	status = "okay";

	flash@0 {

		compatible = "m25p80", "jedec,spi-nor"; /* Micron MT25QU512ABB8ESF */

		#address-cells = <1>;

		#size-cells = <1>;

		reg = <0x0>;

		spi-tx-bus-width = <1>;

		spi-rx-bus-width = <4>;

		spi-max-frequency = <108000000>; /* Based on DC1 spec */

	};

};



&rtc {

	status = "okay";

};

arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts

+14 −0
Original line number Diff line number Diff line
@@ -26,6 +26,7 @@ aliases { 
		rtc0 = &rtc;

		serial0 = &uart0;

		serial1 = &uart1;

		spi0 = &qspi;

	};



	chosen {
@@ -161,6 +162,19 @@ &i2c1 { 
	status = "okay";

};



&qspi {

	status = "okay";

	flash@0 {

		compatible = "m25p80", "jedec,spi-nor"; /* 32MB */

		#address-cells = <1>;

		#size-cells = <1>;

		reg = <0x0>;

		spi-tx-bus-width = <1>;

		spi-rx-bus-width = <4>; /* also DUAL configuration possible */

		spi-max-frequency = <108000000>; /* Based on DC1 spec */

	};

};



&rtc {

	status = "okay";

};

arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts

+15 −0
Original line number Diff line number Diff line
@@ -30,6 +30,7 @@ aliases { 
		serial0 = &uart0;

		serial1 = &uart1;

		serial2 = &dcc;

		spi0 = &qspi;

	};



	chosen {
@@ -934,6 +935,20 @@ &psgtr { 
	clock-names = "ref0", "ref1", "ref2", "ref3";

};



&qspi {

	status = "okay";

	is-dual = <1>;

	flash@0 {

		compatible = "m25p80", "jedec,spi-nor"; /* 32MB */

		#address-cells = <1>;

		#size-cells = <1>;

		reg = <0x0>;

		spi-tx-bus-width = <1>;

		spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */

		spi-max-frequency = <108000000>; /* Based on DC1 spec */

	};

};



&rtc {

	status = "okay";

};