Commit 5710e16a authored by Thierry Reding's avatar Thierry Reding
Browse files

arm64: tegra: Add Tegra234 IOMMUs 



The NVIDIA Tegra234 SoC comes with one single-instance ARM SMMU used by
isochronous memory clients and two dual-instance ARM SMMUs used by non-
isochronous memory clients.

Add the corresponding device tree nodes and hook up existing memory
clients (SDHCI and BPMP).

Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 699349e0

arch/arm64/boot/dts/nvidia/tegra234.dtsi

+426 −0
Original line number Diff line number Diff line
@@ -262,6 +262,7 @@ mmc@3460000 { 
			interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRAB &emc>,

					<&mc TEGRA234_MEMORY_CLIENT_SDMMCWAB &emc>;

			interconnect-names = "dma-mem", "write";

			iommus = <&smmu_niso1 TEGRA234_SID_SDMMC4>;

			nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;

			nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;

			nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
@@ -300,6 +301,148 @@ hsp_top0: hsp@3c00000 { 
			#mbox-cells = <2>;

		};



		smmu_niso1: iommu@8000000 {

			compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500";

			reg = <0x8000000 0x1000000>,

			      <0x7000000 0x1000000>;

			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;

			stream-match-mask = <0x7f80>;

			#global-interrupts = <2>;

			#iommu-cells = <1>;



			nvidia,memory-controller = <&mc>;

			status = "okay";

		};



		hsp_aon: hsp@c150000 {

			compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp";

			reg = <0x0c150000 0x90000>;
@@ -395,6 +538,288 @@ gic: interrupt-controller@f400000 { 
			#interrupt-cells = <3>;

			interrupt-controller;

		};



		smmu_iso: iommu@10000000{

			compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500";

			reg = <0x10000000 0x1000000>;

			interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;

			stream-match-mask = <0x7f80>;

			#global-interrupts = <1>;

			#iommu-cells = <1>;



			nvidia,memory-controller = <&mc>;

			status = "okay";

		};



		smmu_niso0: iommu@12000000 {

			compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500";

			reg = <0x12000000 0x1000000>,

			      <0x11000000 0x1000000>;

			interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;

			stream-match-mask = <0x7f80>;

			#global-interrupts = <2>;

			#iommu-cells = <1>;



			nvidia,memory-controller = <&mc>;

			status = "okay";

		};

	};



	sram@40000000 {
@@ -430,6 +855,7 @@ bpmp: bpmp { 
				<&mc TEGRA234_MEMORY_CLIENT_BPMPDMAR &emc>,

				<&mc TEGRA234_MEMORY_CLIENT_BPMPDMAW &emc>;

		interconnect-names = "read", "write", "dma-mem", "dma-write";

		iommus = <&smmu_niso1 TEGRA234_SID_BPMP>;



		bpmp_i2c: i2c {

			compatible = "nvidia,tegra186-bpmp-i2c";