Commit 5865d252 authored by Biju Das's avatar Biju Das Committed by Geert Uytterhoeven
Browse files

clk: renesas: r9a0{7g04[34],8g045}: Add critical reset entries 



The RZ/G2L SoC family requires DMA resets to be deasserted for routing
some peripheral interrupts to the CPU. Asserting these resets after boot
would silently break interrupt delivery with no driver to restore them.

Mark the DMA resets as critical by adding them to the crit_resets table
in the SoC-specific rzg2l_cpg_info for r9a07g043, r9a07g044, and
r9a08g045, preventing __rzg2l_cpg_assert() from asserting them and
ensuring they are deasserted during probe and resume.

Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Link: https://patch.msgid.link/20260324114329.268249-4-biju.das.jz@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 3d700746

drivers/clk/renesas/r9a07g043-cpg.c

+9 −0
Original line number Diff line number Diff line
@@ -379,6 +379,11 @@ static const unsigned int r9a07g043_crit_mod_clks[] __initconst = { 
	MOD_CLK_BASE + R9A07G043_DMAC_ACLK,

};



static const unsigned int r9a07g043_crit_resets[] = {

	R9A07G043_DMAC_ARESETN,

	R9A07G043_DMAC_RST_ASYNC,

};



#ifdef CONFIG_ARM64

static const unsigned int r9a07g043_no_pm_mod_clks[] = {

	MOD_CLK_BASE + R9A07G043_CRU_SYSCLK,
@@ -420,5 +425,9 @@ const struct rzg2l_cpg_info r9a07g043_cpg_info = { 
	.num_resets = R9A07G043_IAX45_RESETN + 1, /* Last reset ID + 1 */

#endif



	/* Critical Resets */

	.crit_resets = r9a07g043_crit_resets,

	.num_crit_resets = ARRAY_SIZE(r9a07g043_crit_resets),



	.has_clk_mon_regs = true,

};

drivers/clk/renesas/r9a07g044-cpg.c

+13 −0
Original line number Diff line number Diff line
@@ -489,6 +489,11 @@ static const unsigned int r9a07g044_crit_mod_clks[] __initconst = { 
	MOD_CLK_BASE + R9A07G044_DMAC_ACLK,

};



static const unsigned int r9a07g044_crit_resets[] = {

	R9A07G044_DMAC_ARESETN,

	R9A07G044_DMAC_RST_ASYNC,

};



static const unsigned int r9a07g044_no_pm_mod_clks[] = {

	MOD_CLK_BASE + R9A07G044_CRU_SYSCLK,

	MOD_CLK_BASE + R9A07G044_CRU_VCLK,
@@ -519,6 +524,10 @@ const struct rzg2l_cpg_info r9a07g044_cpg_info = { 
	.resets = r9a07g044_resets,

	.num_resets = R9A07G044_TSU_PRESETN + 1, /* Last reset ID + 1 */



	/* Critical Resets */

	.crit_resets = r9a07g044_crit_resets,

	.num_crit_resets = ARRAY_SIZE(r9a07g044_crit_resets),



	.has_clk_mon_regs = true,

};

#endif
@@ -548,6 +557,10 @@ const struct rzg2l_cpg_info r9a07g054_cpg_info = { 
	.resets = r9a07g044_resets,

	.num_resets = R9A07G054_STPAI_ARESETN + 1, /* Last reset ID + 1 */



	/* Critical Resets */

	.crit_resets = r9a07g044_crit_resets,

	.num_crit_resets = ARRAY_SIZE(r9a07g044_crit_resets),



	.has_clk_mon_regs = true,

};

#endif

drivers/clk/renesas/r9a08g045-cpg.c

+9 −0
Original line number Diff line number Diff line
@@ -361,6 +361,11 @@ static const unsigned int r9a08g045_crit_mod_clks[] __initconst = { 
	MOD_CLK_BASE + R9A08G045_VBAT_BCLK,

};



static const unsigned int r9a08g045_crit_resets[] = {

	R9A08G045_DMAC_ARESETN,

	R9A08G045_DMAC_RST_ASYNC,

};



static const unsigned int r9a08g045_no_pm_mod_clks[] = {

	MOD_CLK_BASE + R9A08G045_PCI_CLKL1PM,

};
@@ -389,5 +394,9 @@ const struct rzg2l_cpg_info r9a08g045_cpg_info = { 
	.resets = r9a08g045_resets,

	.num_resets = R9A08G045_VBAT_BRESETN + 1, /* Last reset ID + 1 */



	/* Critical Resets */

	.crit_resets = r9a08g045_crit_resets,

	.num_crit_resets = ARRAY_SIZE(r9a08g045_crit_resets),



	.has_clk_mon_regs = true,

};