+6
−0
Loading
Check potential faults for CR4.CET setting per Intel SDM requirements. CET can be enabled if and only if CR0.WP == 1, i.e. setting CR4.CET == 1 faults if CR0.WP == 0 and setting CR0.WP == 0 fails if CR4.CET == 1. Signed-off-by:Yang Weijiang <weijiang.yang@intel.com> Reviewed-by:
Chao Gao <chao.gao@intel.com> Reviewed-by:
Maxim Levitsky <mlevitsk@redhat.com> Reviewed-by:
Xiaoyao Li <xiaoyao.li@intel.com> Tested-by:
Mathias Krause <minipli@grsecurity.net> Tested-by:
John Allen <john.allen@amd.com> Tested-by:
Rick Edgecombe <rick.p.edgecombe@intel.com> Signed-off-by:
Chao Gao <chao.gao@intel.com> Reviewed-by:
Binbin Wu <binbin.wu@linux.intel.com> Co-developed-by:
Sean Christopherson <seanjc@google.com> Link: https://lore.kernel.org/r/20250919223258.1604852-11-seanjc@google.com Signed-off-by:
Sean Christopherson <seanjc@google.com>