Commit 58825789 authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski Committed by Abhinav Kumar
Browse files

drm/msm/dsi/phy: Protect PHY_CMN_CLK_CFG0 updated from driver side 



PHY_CMN_CLK_CFG0 register is updated by the PHY driver and by two
divider clocks from Common Clock Framework:
devm_clk_hw_register_divider_parent_hw().  Concurrent access by the
clocks side is protected with spinlock, however driver's side in
restoring state is not.  Restoring state is called from
msm_dsi_phy_enable(), so there could be a path leading to concurrent and
conflicting updates with clock framework.

Add missing lock usage on the PHY driver side, encapsulated in its own
function so the code will be still readable.

While shuffling the code, define and use PHY_CMN_CLK_CFG0 bitfields to
make the code more readable and obvious.

Fixes: 1ef7c99d ("drm/msm/dsi: add support for 7nm DSI PHY/PLL")
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: default avatarAbhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/637376/
Link: https://lore.kernel.org/r/20250214-drm-msm-phy-pll-cfg-reg-v3-1-0943b850722c@linaro.org


Signed-off-by: default avatarAbhinav Kumar <quic_abhinavk@quicinc.com>
parent 5e192eef

drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c

+12 −2
Original line number Diff line number Diff line
@@ -372,6 +372,15 @@ static void dsi_pll_enable_pll_bias(struct dsi_pll_7nm *pll) 
	ndelay(250);

}



static void dsi_pll_cmn_clk_cfg0_write(struct dsi_pll_7nm *pll, u32 val)

{

	unsigned long flags;



	spin_lock_irqsave(&pll->postdiv_lock, flags);

	writel(val, pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG0);

	spin_unlock_irqrestore(&pll->postdiv_lock, flags);

}



static void dsi_pll_disable_global_clk(struct dsi_pll_7nm *pll)

{

	u32 data;
@@ -574,8 +583,9 @@ static int dsi_7nm_pll_restore_state(struct msm_dsi_phy *phy) 
	val |= cached->pll_out_div;

	writel(val, pll_7nm->phy->pll_base + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE);



	writel(cached->bit_clk_div | (cached->pix_clk_div << 4),

	       phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG0);

	dsi_pll_cmn_clk_cfg0_write(pll_7nm,

				   DSI_7nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0(cached->bit_clk_div) |

				   DSI_7nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4(cached->pix_clk_div));



	val = readl(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);

	val &= ~0x3;

drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml

+4 −1
Original line number Diff line number Diff line
@@ -9,7 +9,10 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> 
	<reg32 offset="0x00004" name="REVISION_ID1"/>

	<reg32 offset="0x00008" name="REVISION_ID2"/>

	<reg32 offset="0x0000c" name="REVISION_ID3"/>

	<reg32 offset="0x00010" name="CLK_CFG0"/>

	<reg32 offset="0x00010" name="CLK_CFG0">

		<bitfield name="DIV_CTRL_3_0" low="0" high="3" type="uint"/>

		<bitfield name="DIV_CTRL_7_4" low="4" high="7" type="uint"/>

	</reg32>

	<reg32 offset="0x00014" name="CLK_CFG1"/>

	<reg32 offset="0x00018" name="GLBL_CTRL"/>

	<reg32 offset="0x0001c" name="RBUF_CTRL"/>