Commit 589c3357 authored by Ira Weiny's avatar Ira Weiny Committed by Dan Williams
Browse files

PCI/CXL: Export native CXL error reporting control 



CXL _OSC Error Reporting Control is used by the OS to determine if
Firmware has control of various CXL error reporting capabilities
including the event logs.

Expose the result of negotiating CXL Error Reporting Control in struct
pci_host_bridge for consumption by the CXL drivers.

Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Lukas Wunner <lukas@wunner.de>
Cc: linux-pci@vger.kernel.org
Cc: linux-acpi@vger.kernel.org
Signed-off-by: default avatarIra Weiny <ira.weiny@intel.com>
Acked-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: default avatarDan Williams <dan.j.williams@intel.com>
Link: https://lore.kernel.org/r/20221212070627.1372402-2-ira.weiny@intel.com


Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
parent 4a20bc3e

drivers/acpi/pci_root.c

+3 −0
Original line number Diff line number Diff line
@@ -1047,6 +1047,9 @@ struct pci_bus *acpi_pci_root_create(struct acpi_pci_root *root, 
	if (!(root->osc_control_set & OSC_PCI_EXPRESS_DPC_CONTROL))

		host_bridge->native_dpc = 0;



	if (!(root->osc_ext_control_set & OSC_CXL_ERROR_REPORTING_CONTROL))

		host_bridge->native_cxl_error = 0;



	/*

	 * Evaluate the "PCI Boot Configuration" _DSM Function.  If it

	 * exists and returns 0, we must preserve any PCI resource

drivers/pci/probe.c

+1 −0
Original line number Diff line number Diff line
@@ -596,6 +596,7 @@ static void pci_init_host_bridge(struct pci_host_bridge *bridge) 
	bridge->native_ltr = 1;

	bridge->native_dpc = 1;

	bridge->domain_nr = PCI_DOMAIN_NR_NOT_SET;

	bridge->native_cxl_error = 1;



	device_initialize(&bridge->dev);

}

include/linux/pci.h

+1 −0
Original line number Diff line number Diff line
@@ -578,6 +578,7 @@ struct pci_host_bridge { 
	unsigned int	native_pme:1;		/* OS may use PCIe PME */

	unsigned int	native_ltr:1;		/* OS may use PCIe LTR */

	unsigned int	native_dpc:1;		/* OS may use PCIe DPC */

	unsigned int	native_cxl_error:1;	/* OS may use CXL RAS/Events */

	unsigned int	preserve_config:1;	/* Preserve FW resource setup */

	unsigned int	size_windows:1;		/* Enable root bus sizing */

	unsigned int	msi_domain:1;		/* Bridge wants MSI domain */