Commit 58b61fc7 authored by Miquel Raynal's avatar Miquel Raynal Committed by Vinod Koul
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dmaengine: xilinx: xdma: Clarify the logic between cyclic/sg modes 



We support both modes, but they perform totally different taks in the
interrupt handler. Clarify what shall be done in each case.

Signed-off-by: default avatarMiquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/r/20231130111315.729430-3-miquel.raynal@bootlin.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 26ee018f

drivers/dma/xilinx/xdma.c

+14 −17
Original line number Diff line number Diff line
@@ -765,14 +765,10 @@ static irqreturn_t xdma_channel_isr(int irq, void *dev_id) 
		regmap_write(xdev->rmap, xchan->base + XDMA_CHAN_STATUS, st);



		vchan_cyclic_callback(vd);

		goto out;

	}



	} else {

		desc->completed_desc_num += complete_desc_num;



	/*

	 * if all data blocks are transferred, remove and complete the request

	 */

		/* if all data blocks are transferred, remove and complete the request */

		if (desc->completed_desc_num == desc->desc_num) {

			list_del(&vd->node);

			vchan_cookie_complete(vd);
@@ -783,8 +779,9 @@ static irqreturn_t xdma_channel_isr(int irq, void *dev_id) 
		    complete_desc_num != XDMA_DESC_BLOCK_NUM * XDMA_DESC_ADJACENT)

			goto out;



	/* transfer the rest of data (SG only) */

		/* transfer the rest of data */

		xdma_xfer_start(xchan);

	}



out:

	spin_unlock(&xchan->vchan.lock);