Commit 58ccd7e8 authored by Michal Simek's avatar Michal Simek
Browse files

arm64: zynqmp: List reset property for ethernet phy 



Add information about reset gpio for ethernet phy in case someone wants to
use it.

Signed-off-by: default avatarMichal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/e153f0cda37a2a6ea1c6e11fb0a4af1d400f29e2.1623684253.git.michal.simek@xilinx.com
parent d65ec93f

arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts

+1 −0
Original line number Diff line number Diff line
@@ -204,6 +204,7 @@ phy0: ethernet-phy@21 { 
		ti,tx-internal-delay = <0xa>;

		ti,fifo-depth = <0x1>;

		ti,dp83867-rxctrl-strap-quirk;

		/* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */

	};

};

arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts

+2 −1
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ 
/*

 * dts file for Xilinx ZynqMP ZCU102 RevB

 *

 * (C) Copyright 2016 - 2018, Xilinx, Inc.

 * (C) Copyright 2016 - 2021, Xilinx, Inc.

 *

 * Michal Simek <michal.simek@xilinx.com>

 */
@@ -22,6 +22,7 @@ phyc: ethernet-phy@c { 
		ti,tx-internal-delay = <0xa>;

		ti,fifo-depth = <0x1>;

		ti,dp83867-rxctrl-strap-quirk;

		/* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */

	};

	/* Cleanup from RevA */

	/delete-node/ ethernet-phy@21;