Commit 592c5b80 authored by Bhuvanachandra Pinninti's avatar Bhuvanachandra Pinninti Committed by Alex Deucher
Browse files

drm/amd/display: Migrate HUBBUB register access from hwseq to hubbub component. 



[why]
Direct HUBBUB register access in the hwseq layer was creating register conflicts.

[how]
Migrated HUBBUB registers from hwseq to the hubbub component.

Reviewed-by: default avatarMartin Leung <martin.leung@amd.com>
Signed-off-by: default avatarBhuvanachandra Pinninti <bpinnint@amd.com>
Signed-off-by: default avatarAurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: default avatarDan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ba448f9e

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

+18 −0
Original line number Diff line number Diff line
@@ -944,3 +944,21 @@ void hubbub1_construct(struct hubbub *hubbub, 
		hubbub1->debug_test_index_pstate = 0xB;

}



void dcn10_hubbub_global_timer_enable(struct hubbub *hubbub, bool enable, uint32_t refdiv)

{

	struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub);



	if (refdiv > 0)

		REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, refdiv);



	REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, enable ? 1 : 0);

}



void dcn10_hubbub_read_fb_aperture(struct hubbub *hubbub, uint32_t *fb_base_value, uint32_t *fb_offset_value)

{

	struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub);



	REG_GET(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, fb_base_value);

	REG_GET(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, fb_offset_value);

}

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

+4 −0
Original line number Diff line number Diff line
@@ -519,4 +519,8 @@ bool hubbub1_program_pstate_watermarks( 
		unsigned int refclk_mhz,

		bool safe_to_lower);



void dcn10_hubbub_global_timer_enable(struct hubbub *hubbub, bool enable, uint32_t refdiv);



void dcn10_hubbub_read_fb_aperture(struct hubbub *hubbub, uint32_t *fb_base_value, uint32_t *fb_offset_value);



#endif

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

+1 −2
Original line number Diff line number Diff line
@@ -2678,8 +2678,7 @@ static void mmhub_read_vm_context0_settings(struct dcn10_hubp *hubp1, 
	uint32_t fb_base_value;

	uint32_t fb_offset_value;



	REG_GET(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, &fb_base_value);

	REG_GET(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, &fb_offset_value);

	dcn10_hubbub_read_fb_aperture(hws->ctx->dc->res_pool->hubbub, &fb_base_value, &fb_offset_value);



	REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,

			PAGE_DIRECTORY_ENTRY_HI32, &vm0->pte_base.high_part);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

+2 −2
Original line number Diff line number Diff line
@@ -46,6 +46,7 @@ 
#include "dchubbub.h"

#include "reg_helper.h"

#include "dcn10/dcn10_cm_common.h"

#include "dcn10/dcn10_hubbub.h"

#include "vm_helper.h"

#include "dccg.h"

#include "dc_dmub_srv.h"
@@ -3153,8 +3154,7 @@ void dcn20_fpga_init_hw(struct dc *dc) 
	REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF);

	REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF);



	REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2);

	REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);

	dcn10_hubbub_global_timer_enable(dc->res_pool->hubbub, true, 2);

	if (REG(REFCLK_CNTL))

		REG_WRITE(REFCLK_CNTL, 0);

	//

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

+1 −0
Original line number Diff line number Diff line
@@ -39,6 +39,7 @@ 
#include "dccg.h"

#include "clk_mgr.h"

#include "reg_helper.h"

#include "dcn10/dcn10_hubbub.h"



#define CTX \

	hws->ctx