Commit 593bcf68 authored by Linus Walleij's avatar Linus Walleij
Browse files

Merge tag 'intel-pinctrl-v6.7-1' of... 

Merge tag 'intel-pinctrl-v6.7-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel

 into devel

intel-pinctrl for v6.7-1

* Merge "Drop runtime PM support for Baytrail and Lynxpoint pinctrl" (Raag)
* Small improvements here and there in the Intel pin control drivers (Raag)
* Switch to RAII for locking in the Intel core and Cherry View drivers
* Enable non-ACPI enumeration in the Intel Denverton driver
* Use MODULE_DEVICE_TABLE() instead of MODULE_ALIAS() in a couple of drivers
* Introduce array_size.h and use in in the Intel pin control drivers

The following is an automated git shortlog grouped by driver:

baytrail:
 -  Replace kernel.h by what is actually being used
 -  drop runtime PM support
 -  fix debounce disable case

broxton:
 -  Replace MODULE_ALIAS() with MODULE_DEVICE_TABLE()

cherryview:
 -  reduce scope of PIN_CONFIG_BIAS_HIGH_IMPEDANCE case
 -  Convert to platform remove callback returning void
 -  Simplify code with cleanup helpers
 -  Avoid duplicated I/O
 -  Replace kernel.h by what is actually being used

denverton:
 -  Replace MODULE_ALIAS() with MODULE_DEVICE_TABLE()
 -  Enable platform device in the absence of ACPI enumeration

intel:
 -  fetch community only when we need it
 -  refine intel_config_set_pull() function
 -  Replace kernel.h by what is actually being used
 -  Simplify code with cleanup helpers

lynxpoint:
 -  Replace kernel.h by what is actually being used
 -  drop runtime PM support

merrifield:
 -  Replace kernel.h by what is actually being used

moorefield:
 -  Replace kernel.h by what is actually being used
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parents 30d75d3c 8d751da9

drivers/pinctrl/core.c

+1 −1
Original line number Diff line number Diff line
@@ -12,12 +12,12 @@ 
 */

#define pr_fmt(fmt) "pinctrl core: " fmt



#include <linux/array_size.h>

#include <linux/debugfs.h>

#include <linux/device.h>

#include <linux/err.h>

#include <linux/export.h>

#include <linux/init.h>

#include <linux/kernel.h>

#include <linux/kref.h>

#include <linux/list.h>

#include <linux/seq_file.h>

drivers/pinctrl/intel/pinctrl-baytrail.c

+12 −20
Original line number Diff line number Diff line
@@ -7,16 +7,16 @@ 
 */



#include <linux/acpi.h>

#include <linux/array_size.h>

#include <linux/bitops.h>

#include <linux/gpio/driver.h>

#include <linux/init.h>

#include <linux/interrupt.h>

#include <linux/io.h>

#include <linux/kernel.h>

#include <linux/module.h>

#include <linux/types.h>

#include <linux/platform_device.h>

#include <linux/pm_runtime.h>

#include <linux/pm.h>

#include <linux/property.h>

#include <linux/seq_file.h>

#include <linux/string_helpers.h>
@@ -722,8 +722,6 @@ static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev, 


	raw_spin_unlock_irqrestore(&byt_lock, flags);



	pm_runtime_get(vg->dev);



	return 0;

}
@@ -734,7 +732,6 @@ static void byt_gpio_disable_free(struct pinctrl_dev *pctl_dev, 
	struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);



	byt_gpio_clear_triggering(vg, offset);

	pm_runtime_put(vg->dev);

}



static void byt_gpio_direct_irq_check(struct intel_pinctrl *vg,
@@ -983,11 +980,18 @@ static int byt_pin_config_set(struct pinctrl_dev *pctl_dev, 


			break;

		case PIN_CONFIG_INPUT_DEBOUNCE:

			if (arg)

			if (arg) {

				conf |= BYT_DEBOUNCE_EN;

			else

			} else {

				conf &= ~BYT_DEBOUNCE_EN;



				/*

				 * No need to update the pulse value.

				 * Debounce is going to be disabled.

				 */

				break;

			}



			switch (arg) {

			case 375:

				db_pulse = BYT_DEBOUNCE_PULSE_375US;
@@ -1654,7 +1658,6 @@ static int byt_pinctrl_probe(struct platform_device *pdev) 
		return ret;



	platform_set_drvdata(pdev, vg);

	pm_runtime_enable(dev);



	return 0;

}
@@ -1743,26 +1746,15 @@ static int byt_gpio_resume(struct device *dev) 
	return 0;

}



static int byt_gpio_runtime_suspend(struct device *dev)

{

	return 0;

}



static int byt_gpio_runtime_resume(struct device *dev)

{

	return 0;

}



static const struct dev_pm_ops byt_gpio_pm_ops = {

	LATE_SYSTEM_SLEEP_PM_OPS(byt_gpio_suspend, byt_gpio_resume)

	RUNTIME_PM_OPS(byt_gpio_runtime_suspend, byt_gpio_runtime_resume, NULL)

};



static struct platform_driver byt_gpio_driver = {

	.probe          = byt_pinctrl_probe,

	.driver         = {

		.name			= "byt_gpio",

		.pm			= pm_ptr(&byt_gpio_pm_ops),

		.pm			= pm_sleep_ptr(&byt_gpio_pm_ops),

		.acpi_match_table	= byt_gpio_acpi_match,

		.suppress_bind_attrs	= true,

	},

drivers/pinctrl/intel/pinctrl-broxton.c

+1 −2
Original line number Diff line number Diff line
@@ -998,6 +998,7 @@ static const struct platform_device_id bxt_pinctrl_platform_ids[] = { 
	{ "broxton-pinctrl", (kernel_ulong_t)bxt_pinctrl_soc_data },

	{ }

};

MODULE_DEVICE_TABLE(platform, bxt_pinctrl_platform_ids);



static INTEL_PINCTRL_PM_OPS(bxt_pinctrl_pm_ops);
@@ -1026,6 +1027,4 @@ module_exit(bxt_pinctrl_exit); 
MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");

MODULE_DESCRIPTION("Intel Broxton SoC pinctrl/GPIO driver");

MODULE_LICENSE("GPL v2");

MODULE_ALIAS("platform:apollolake-pinctrl");

MODULE_ALIAS("platform:broxton-pinctrl");

MODULE_IMPORT_NS(PINCTRL_INTEL);

drivers/pinctrl/intel/pinctrl-cherryview.c

+57 −100
Original line number Diff line number Diff line
@@ -11,9 +11,10 @@ 
 */



#include <linux/acpi.h>

#include <linux/array_size.h>

#include <linux/cleanup.h>

#include <linux/dmi.h>

#include <linux/gpio/driver.h>

#include <linux/kernel.h>

#include <linux/module.h>

#include <linux/platform_device.h>

#include <linux/seq_file.h>
@@ -612,26 +613,26 @@ static void chv_writel(struct intel_pinctrl *pctrl, unsigned int pin, unsigned i 
}



/* When Pad Cfg is locked, driver can only change GPIOTXState or GPIORXState */

static bool chv_pad_is_locked(u32 ctrl1)

{

	return ctrl1 & CHV_PADCTRL1_CFGLOCK;

}



static bool chv_pad_locked(struct intel_pinctrl *pctrl, unsigned int offset)

{

	return chv_readl(pctrl, offset, CHV_PADCTRL1) & CHV_PADCTRL1_CFGLOCK;

	return chv_pad_is_locked(chv_readl(pctrl, offset, CHV_PADCTRL1));

}



static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,

			     unsigned int offset)

{

	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);

	unsigned long flags;

	u32 ctrl0, ctrl1;

	bool locked;



	raw_spin_lock_irqsave(&chv_lock, flags);



	scoped_guard(raw_spinlock_irqsave, &chv_lock) {

		ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0);

		ctrl1 = chv_readl(pctrl, offset, CHV_PADCTRL1);

	locked = chv_pad_locked(pctrl, offset);



	raw_spin_unlock_irqrestore(&chv_lock, flags);

	}



	if (ctrl0 & CHV_PADCTRL0_GPIOEN) {

		seq_puts(s, "GPIO ");
@@ -646,7 +647,7 @@ static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 


	seq_printf(s, "0x%08x 0x%08x", ctrl0, ctrl1);



	if (locked)

	if (chv_pad_is_locked(ctrl1))

		seq_puts(s, " [LOCKED]");

}
@@ -663,17 +664,15 @@ static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev, 
	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);

	struct device *dev = pctrl->dev;

	const struct intel_pingroup *grp;

	unsigned long flags;

	int i;



	grp = &pctrl->soc->groups[group];



	raw_spin_lock_irqsave(&chv_lock, flags);

	guard(raw_spinlock_irqsave)(&chv_lock);



	/* Check first that the pad is not locked */

	for (i = 0; i < grp->grp.npins; i++) {

		if (chv_pad_locked(pctrl, grp->grp.pins[i])) {

			raw_spin_unlock_irqrestore(&chv_lock, flags);

			dev_warn(dev, "unable to set mode for locked pin %u\n", grp->grp.pins[i]);

			return -EBUSY;

		}
@@ -713,8 +712,6 @@ static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev, 
			invert_oe ? "" : "not ");

	}



	raw_spin_unlock_irqrestore(&chv_lock, flags);



	return 0;

}
@@ -745,16 +742,14 @@ static int chv_gpio_request_enable(struct pinctrl_dev *pctldev, 
				   unsigned int offset)

{

	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);

	unsigned long flags;

	u32 value;



	raw_spin_lock_irqsave(&chv_lock, flags);

	guard(raw_spinlock_irqsave)(&chv_lock);



	if (chv_pad_locked(pctrl, offset)) {

		value = chv_readl(pctrl, offset, CHV_PADCTRL0);

		if (!(value & CHV_PADCTRL0_GPIOEN)) {

			/* Locked so cannot enable */

			raw_spin_unlock_irqrestore(&chv_lock, flags);

			return -EBUSY;

		}

	} else {
@@ -789,8 +784,6 @@ static int chv_gpio_request_enable(struct pinctrl_dev *pctldev, 
		chv_writel(pctrl, offset, CHV_PADCTRL0, value);

	}



	raw_spin_unlock_irqrestore(&chv_lock, flags);



	return 0;

}
@@ -799,14 +792,13 @@ static void chv_gpio_disable_free(struct pinctrl_dev *pctldev, 
				  unsigned int offset)

{

	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);

	unsigned long flags;



	raw_spin_lock_irqsave(&chv_lock, flags);

	guard(raw_spinlock_irqsave)(&chv_lock);



	if (!chv_pad_locked(pctrl, offset))

		chv_gpio_clear_triggering(pctrl, offset);

	if (chv_pad_locked(pctrl, offset))

		return;



	raw_spin_unlock_irqrestore(&chv_lock, flags);

	chv_gpio_clear_triggering(pctrl, offset);

}



static int chv_gpio_set_direction(struct pinctrl_dev *pctldev,
@@ -814,10 +806,9 @@ static int chv_gpio_set_direction(struct pinctrl_dev *pctldev, 
				  unsigned int offset, bool input)

{

	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);

	unsigned long flags;

	u32 ctrl0;



	raw_spin_lock_irqsave(&chv_lock, flags);

	guard(raw_spinlock_irqsave)(&chv_lock);



	ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0) & ~CHV_PADCTRL0_GPIOCFG_MASK;

	if (input)
@@ -826,8 +817,6 @@ static int chv_gpio_set_direction(struct pinctrl_dev *pctldev, 
		ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPO << CHV_PADCTRL0_GPIOCFG_SHIFT;

	chv_writel(pctrl, offset, CHV_PADCTRL0, ctrl0);



	raw_spin_unlock_irqrestore(&chv_lock, flags);



	return 0;

}
@@ -846,15 +835,14 @@ static int chv_config_get(struct pinctrl_dev *pctldev, unsigned int pin, 
{

	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);

	enum pin_config_param param = pinconf_to_config_param(*config);

	unsigned long flags;

	u32 ctrl0, ctrl1;

	u16 arg = 0;

	u32 term;



	raw_spin_lock_irqsave(&chv_lock, flags);

	scoped_guard(raw_spinlock_irqsave, &chv_lock) {

		ctrl0 = chv_readl(pctrl, pin, CHV_PADCTRL0);

		ctrl1 = chv_readl(pctrl, pin, CHV_PADCTRL1);

	raw_spin_unlock_irqrestore(&chv_lock, flags);

	}



	term = (ctrl0 & CHV_PADCTRL0_TERM_MASK) >> CHV_PADCTRL0_TERM_SHIFT;
@@ -906,6 +894,7 @@ static int chv_config_get(struct pinctrl_dev *pctldev, unsigned int pin, 
			return -EINVAL;



		break;

	}



	case PIN_CONFIG_DRIVE_PUSH_PULL:

		if (ctrl1 & CHV_PADCTRL1_ODEN)
@@ -916,7 +905,6 @@ static int chv_config_get(struct pinctrl_dev *pctldev, unsigned int pin, 
		if (!(ctrl1 & CHV_PADCTRL1_ODEN))

			return -EINVAL;

		break;

	}



	default:

		return -ENOTSUPP;
@@ -929,10 +917,10 @@ static int chv_config_get(struct pinctrl_dev *pctldev, unsigned int pin, 
static int chv_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin,

			       enum pin_config_param param, u32 arg)

{

	unsigned long flags;

	u32 ctrl0, pull;



	raw_spin_lock_irqsave(&chv_lock, flags);

	guard(raw_spinlock_irqsave)(&chv_lock);



	ctrl0 = chv_readl(pctrl, pin, CHV_PADCTRL0);



	switch (param) {
@@ -955,7 +943,6 @@ static int chv_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin, 
			pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT;

			break;

		default:

			raw_spin_unlock_irqrestore(&chv_lock, flags);

			return -EINVAL;

		}
@@ -973,7 +960,6 @@ static int chv_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin, 
			pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT;

			break;

		default:

			raw_spin_unlock_irqrestore(&chv_lock, flags);

			return -EINVAL;

		}
@@ -981,12 +967,10 @@ static int chv_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin, 
		break;



	default:

		raw_spin_unlock_irqrestore(&chv_lock, flags);

		return -EINVAL;

	}



	chv_writel(pctrl, pin, CHV_PADCTRL0, ctrl0);

	raw_spin_unlock_irqrestore(&chv_lock, flags);



	return 0;

}
@@ -994,10 +978,10 @@ static int chv_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin, 
static int chv_config_set_oden(struct intel_pinctrl *pctrl, unsigned int pin,

			       bool enable)

{

	unsigned long flags;

	u32 ctrl1;



	raw_spin_lock_irqsave(&chv_lock, flags);

	guard(raw_spinlock_irqsave)(&chv_lock);



	ctrl1 = chv_readl(pctrl, pin, CHV_PADCTRL1);



	if (enable)
@@ -1006,7 +990,6 @@ static int chv_config_set_oden(struct intel_pinctrl *pctrl, unsigned int pin, 
		ctrl1 &= ~CHV_PADCTRL1_ODEN;



	chv_writel(pctrl, pin, CHV_PADCTRL1, ctrl1);

	raw_spin_unlock_irqrestore(&chv_lock, flags);



	return 0;

}
@@ -1116,12 +1099,10 @@ static struct pinctrl_desc chv_pinctrl_desc = { 
static int chv_gpio_get(struct gpio_chip *chip, unsigned int offset)

{

	struct intel_pinctrl *pctrl = gpiochip_get_data(chip);

	unsigned long flags;

	u32 ctrl0, cfg;



	raw_spin_lock_irqsave(&chv_lock, flags);

	scoped_guard(raw_spinlock_irqsave, &chv_lock)

		ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0);

	raw_spin_unlock_irqrestore(&chv_lock, flags);



	cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;

	cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
@@ -1134,10 +1115,9 @@ static int chv_gpio_get(struct gpio_chip *chip, unsigned int offset) 
static void chv_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)

{

	struct intel_pinctrl *pctrl = gpiochip_get_data(chip);

	unsigned long flags;

	u32 ctrl0;



	raw_spin_lock_irqsave(&chv_lock, flags);

	guard(raw_spinlock_irqsave)(&chv_lock);



	ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0);
@@ -1147,19 +1127,15 @@ static void chv_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) 
		ctrl0 &= ~CHV_PADCTRL0_GPIOTXSTATE;



	chv_writel(pctrl, offset, CHV_PADCTRL0, ctrl0);



	raw_spin_unlock_irqrestore(&chv_lock, flags);

}



static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)

{

	struct intel_pinctrl *pctrl = gpiochip_get_data(chip);

	u32 ctrl0, direction;

	unsigned long flags;



	raw_spin_lock_irqsave(&chv_lock, flags);

	scoped_guard(raw_spinlock_irqsave, &chv_lock)

		ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0);

	raw_spin_unlock_irqrestore(&chv_lock, flags);



	direction = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;

	direction >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
@@ -1200,23 +1176,20 @@ static void chv_gpio_irq_ack(struct irq_data *d) 
	irq_hw_number_t hwirq = irqd_to_hwirq(d);

	u32 intr_line;



	raw_spin_lock(&chv_lock);

	guard(raw_spinlock)(&chv_lock);



	intr_line = chv_readl(pctrl, hwirq, CHV_PADCTRL0);

	intr_line &= CHV_PADCTRL0_INTSEL_MASK;

	intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT;

	chv_pctrl_writel(pctrl, CHV_INTSTAT, BIT(intr_line));



	raw_spin_unlock(&chv_lock);

}



static void chv_gpio_irq_mask_unmask(struct gpio_chip *gc, irq_hw_number_t hwirq, bool mask)

{

	struct intel_pinctrl *pctrl = gpiochip_get_data(gc);

	u32 value, intr_line;

	unsigned long flags;



	raw_spin_lock_irqsave(&chv_lock, flags);

	guard(raw_spinlock_irqsave)(&chv_lock);



	intr_line = chv_readl(pctrl, hwirq, CHV_PADCTRL0);

	intr_line &= CHV_PADCTRL0_INTSEL_MASK;
@@ -1228,8 +1201,6 @@ static void chv_gpio_irq_mask_unmask(struct gpio_chip *gc, irq_hw_number_t hwirq 
	else

		value |= BIT(intr_line);

	chv_pctrl_writel(pctrl, CHV_INTMASK, value);



	raw_spin_unlock_irqrestore(&chv_lock, flags);

}



static void chv_gpio_irq_mask(struct irq_data *d)
@@ -1254,7 +1225,15 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d) 
{

	/*

	 * Check if the interrupt has been requested with 0 as triggering

	 * type. In that case it is assumed that the current values

	 * type. If not, bail out, ...

	 */

	if (irqd_get_trigger_type(d) != IRQ_TYPE_NONE) {

		chv_gpio_irq_unmask(d);

		return 0;

	}



	/*

	 * ...otherwise it is assumed that the current values

	 * programmed to the hardware are used (e.g BIOS configured

	 * defaults).

	 *
@@ -1262,17 +1241,15 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d) 
	 * read back the values from hardware now, set correct flow handler

	 * and update mappings before the interrupt is being used.

	 */

	if (irqd_get_trigger_type(d) == IRQ_TYPE_NONE) {

	scoped_guard(raw_spinlock_irqsave, &chv_lock) {

		struct gpio_chip *gc = irq_data_get_irq_chip_data(d);

		struct intel_pinctrl *pctrl = gpiochip_get_data(gc);

		struct device *dev = pctrl->dev;

		struct intel_community_context *cctx = &pctrl->context.communities[0];

		irq_hw_number_t hwirq = irqd_to_hwirq(d);

		irq_flow_handler_t handler;

		unsigned long flags;

		u32 intsel, value;



		raw_spin_lock_irqsave(&chv_lock, flags);

		intsel = chv_readl(pctrl, hwirq, CHV_PADCTRL0);

		intsel &= CHV_PADCTRL0_INTSEL_MASK;

		intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
@@ -1289,7 +1266,6 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d) 
				intsel, hwirq);

			cctx->intr_lines[intsel] = hwirq;

		}

		raw_spin_unlock_irqrestore(&chv_lock, flags);

	}



	chv_gpio_irq_unmask(d);
@@ -1354,17 +1330,14 @@ static int chv_gpio_irq_type(struct irq_data *d, unsigned int type) 
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);

	struct intel_pinctrl *pctrl = gpiochip_get_data(gc);

	irq_hw_number_t hwirq = irqd_to_hwirq(d);

	unsigned long flags;

	u32 value;

	int ret;



	raw_spin_lock_irqsave(&chv_lock, flags);

	guard(raw_spinlock_irqsave)(&chv_lock);



	ret = chv_gpio_set_intr_line(pctrl, hwirq);

	if (ret) {

		raw_spin_unlock_irqrestore(&chv_lock, flags);

	if (ret)

		return ret;

	}



	/*

	 * Pins which can be used as shared interrupt are configured in
@@ -1405,8 +1378,6 @@ static int chv_gpio_irq_type(struct irq_data *d, unsigned int type) 
	else if (type & IRQ_TYPE_LEVEL_MASK)

		irq_set_handler_locked(d, handle_level_irq);



	raw_spin_unlock_irqrestore(&chv_lock, flags);



	return 0;

}
@@ -1430,14 +1401,12 @@ static void chv_gpio_irq_handler(struct irq_desc *desc) 
	struct intel_community_context *cctx = &pctrl->context.communities[0];

	struct irq_chip *chip = irq_desc_get_chip(desc);

	unsigned long pending;

	unsigned long flags;

	u32 intr_line;



	chained_irq_enter(chip, desc);



	raw_spin_lock_irqsave(&chv_lock, flags);

	scoped_guard(raw_spinlock_irqsave, &chv_lock)

		pending = chv_pctrl_readl(pctrl, CHV_INTSTAT);

	raw_spin_unlock_irqrestore(&chv_lock, flags);



	for_each_set_bit(intr_line, &pending, community->nirqs) {

		unsigned int offset;
@@ -1626,21 +1595,17 @@ static acpi_status chv_pinctrl_mmio_access_handler(u32 function, 
	void *handler_context, void *region_context)

{

	struct intel_pinctrl *pctrl = region_context;

	unsigned long flags;

	acpi_status ret = AE_OK;



	raw_spin_lock_irqsave(&chv_lock, flags);

	guard(raw_spinlock_irqsave)(&chv_lock);



	if (function == ACPI_WRITE)

		chv_pctrl_writel(pctrl, address, *value);

	else if (function == ACPI_READ)

		*value = chv_pctrl_readl(pctrl, address);

	else

		ret = AE_BAD_PARAMETER;

		return AE_BAD_PARAMETER;



	raw_spin_unlock_irqrestore(&chv_lock, flags);



	return ret;

	return AE_OK;

}



static int chv_pinctrl_probe(struct platform_device *pdev)
@@ -1728,7 +1693,7 @@ static int chv_pinctrl_probe(struct platform_device *pdev) 
	return 0;

}



static int chv_pinctrl_remove(struct platform_device *pdev)

static void chv_pinctrl_remove(struct platform_device *pdev)

{

	struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);

	const struct intel_community *community = &pctrl->communities[0];
@@ -1736,18 +1701,15 @@ static int chv_pinctrl_remove(struct platform_device *pdev) 
	acpi_remove_address_space_handler(ACPI_HANDLE(&pdev->dev),

					  community->acpi_space_id,

					  chv_pinctrl_mmio_access_handler);



	return 0;

}



static int chv_pinctrl_suspend_noirq(struct device *dev)

{

	struct intel_pinctrl *pctrl = dev_get_drvdata(dev);

	struct intel_community_context *cctx = &pctrl->context.communities[0];

	unsigned long flags;

	int i;



	raw_spin_lock_irqsave(&chv_lock, flags);

	guard(raw_spinlock_irqsave)(&chv_lock);



	cctx->saved_intmask = chv_pctrl_readl(pctrl, CHV_INTMASK);
@@ -1765,8 +1727,6 @@ static int chv_pinctrl_suspend_noirq(struct device *dev) 
		ctx->padctrl1 = chv_readl(pctrl, desc->number, CHV_PADCTRL1);

	}



	raw_spin_unlock_irqrestore(&chv_lock, flags);



	return 0;

}
@@ -1774,10 +1734,9 @@ static int chv_pinctrl_resume_noirq(struct device *dev) 
{

	struct intel_pinctrl *pctrl = dev_get_drvdata(dev);

	struct intel_community_context *cctx = &pctrl->context.communities[0];

	unsigned long flags;

	int i;



	raw_spin_lock_irqsave(&chv_lock, flags);

	guard(raw_spinlock_irqsave)(&chv_lock);



	/*

	 * Mask all interrupts before restoring per-pin configuration
@@ -1819,8 +1778,6 @@ static int chv_pinctrl_resume_noirq(struct device *dev) 
	chv_pctrl_writel(pctrl, CHV_INTSTAT, 0xffff);

	chv_pctrl_writel(pctrl, CHV_INTMASK, cctx->saved_intmask);



	raw_spin_unlock_irqrestore(&chv_lock, flags);



	return 0;

}
@@ -1835,7 +1792,7 @@ MODULE_DEVICE_TABLE(acpi, chv_pinctrl_acpi_match); 


static struct platform_driver chv_pinctrl_driver = {

	.probe = chv_pinctrl_probe,

	.remove = chv_pinctrl_remove,

	.remove_new = chv_pinctrl_remove,

	.driver = {

		.name = "cherryview-pinctrl",

		.pm = pm_sleep_ptr(&chv_pinctrl_pm_ops),

drivers/pinctrl/intel/pinctrl-denverton.c

+7 −0
Original line number Diff line number Diff line
@@ -257,6 +257,12 @@ static const struct acpi_device_id dnv_pinctrl_acpi_match[] = { 
};

MODULE_DEVICE_TABLE(acpi, dnv_pinctrl_acpi_match);



static const struct platform_device_id dnv_pinctrl_platform_ids[] = {

	{ "denverton-pinctrl", (kernel_ulong_t)&dnv_soc_data },

	{ }

};

MODULE_DEVICE_TABLE(platform, dnv_pinctrl_platform_ids);



static struct platform_driver dnv_pinctrl_driver = {

	.probe = intel_pinctrl_probe_by_hid,

	.driver = {
@@ -264,6 +270,7 @@ static struct platform_driver dnv_pinctrl_driver = { 
		.acpi_match_table = dnv_pinctrl_acpi_match,

		.pm = &dnv_pinctrl_pm_ops,

	},

	.id_table = dnv_pinctrl_platform_ids,

};



static int __init dnv_pinctrl_init(void)