Commit 593f1dd4 authored by Konrad Dybcio's avatar Konrad Dybcio Committed by Rob Clark
Browse files

drm/msm/a6xx: Fix A702 UBWC mode 



UBWC_MODE is a one-bit-wide field, so a value of 2 is obviously bogus.

Replace it with the correct value (0).

Fixes: 18397519 ("drm/msm/adreno: Add A702 support")
Reported-by: default avatarConnor Abbott <cwabbott0@gmail.com>
Closes: https://lore.kernel.org/linux-arm-msm/CACu1E7FTN=kwaDJMNiTmFspALzj2+Q-nvsN5ugi=vz4RdUGvGw@mail.gmail.com/


Signed-off-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/597359/


Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
parent 71d9b458

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

+1 −1
Original line number Diff line number Diff line
@@ -547,7 +547,7 @@ static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu) 
	if (adreno_is_a702(gpu)) {

		gpu->ubwc_config.highest_bank_bit = 14;

		gpu->ubwc_config.min_acc_len = 1;

		gpu->ubwc_config.ubwc_mode = 2;

		gpu->ubwc_config.ubwc_mode = 0;

	}

}