Commit 5949d419 authored by Alistair Popple's avatar Alistair Popple Committed by Alexandre Courbot
Browse files

gpu: nova-core: gsp: Boot GSP 



Boot the GSP to the RISC-V active state. Completing the boot requires
running the CPU sequencer which will be added in a future commit.

Reviewed-by: default avatarLyude Paul <lyude@redhat.com>
Signed-off-by: default avatarAlistair Popple <apopple@nvidia.com>
Signed-off-by: default avatarAlexandre Courbot <acourbot@nvidia.com>
Message-ID: <20251110-gsp_boot-v9-15-8ae4058e3c0e@nvidia.com>
parent 945c1eee

drivers/gpu/nova-core/falcon.rs

+0 −2
Original line number Diff line number Diff line
@@ -616,14 +616,12 @@ pub(crate) fn signature_reg_fuse_version( 
    /// Check if the RISC-V core is active.

    ///

    /// Returns `true` if the RISC-V core is active, `false` otherwise.

    #[expect(unused)]

    pub(crate) fn is_riscv_active(&self, bar: &Bar0) -> bool {

        let cpuctl = regs::NV_PRISCV_RISCV_CPUCTL::read(bar, &E::ID);

        cpuctl.active_stat()

    }



    /// Write the application version to the OS register.

    #[expect(dead_code)]

    pub(crate) fn write_os_version(&self, bar: &Bar0, app_version: u32) {

        regs::NV_PFALCON_FALCON_OS::default()

            .set_value(app_version)

drivers/gpu/nova-core/firmware/riscv.rs

+1 −2
Original line number Diff line number Diff line
@@ -57,7 +57,6 @@ fn new(bin_fw: &BinFirmware<'_>) -> Result<Self> { 
}



/// A parsed firmware for a RISC-V core, ready to be loaded and run.

#[expect(unused)]

pub(crate) struct RiscvFirmware {

    /// Offset at which the code starts in the firmware image.

    pub(crate) code_offset: u32,
@@ -66,7 +65,7 @@ pub(crate) struct RiscvFirmware { 
    /// Offset at which the manifest starts in the firmware image.

    pub(crate) manifest_offset: u32,

    /// Application version.

    app_version: u32,

    pub(crate) app_version: u32,

    /// Device-mapped firmware image.

    pub(crate) ucode: DmaObject,

}

drivers/gpu/nova-core/gsp/boot.rs

+63 −2
Original line number Diff line number Diff line
@@ -4,8 +4,10 @@ 
    device,

    dma::CoherentAllocation,

    dma_write,

    io::poll::read_poll_timeout,

    pci,

    prelude::*, //

    prelude::*,

    time::Delta, //

};



use crate::{
@@ -143,7 +145,7 @@ pub(crate) fn boot( 


        Self::run_fwsec_frts(dev, gsp_falcon, bar, &bios, &fb_layout)?;



        let _booter_loader = BooterFirmware::new(

        let booter_loader = BooterFirmware::new(

            dev,

            BooterKind::Loader,

            chipset,
@@ -160,6 +162,65 @@ pub(crate) fn boot( 
            .send_command(bar, commands::SetSystemInfo::new(pdev))?;

        self.cmdq.send_command(bar, commands::SetRegistry::new())?;



        gsp_falcon.reset(bar)?;

        let libos_handle = self.libos.dma_handle();

        let (mbox0, mbox1) = gsp_falcon.boot(

            bar,

            Some(libos_handle as u32),

            Some((libos_handle >> 32) as u32),

        )?;

        dev_dbg!(

            pdev.as_ref(),

            "GSP MBOX0: {:#x}, MBOX1: {:#x}\n",

            mbox0,

            mbox1

        );



        dev_dbg!(

            pdev.as_ref(),

            "Using SEC2 to load and run the booter_load firmware...\n"

        );



        sec2_falcon.reset(bar)?;

        sec2_falcon.dma_load(bar, &booter_loader)?;

        let wpr_handle = wpr_meta.dma_handle();

        let (mbox0, mbox1) = sec2_falcon.boot(

            bar,

            Some(wpr_handle as u32),

            Some((wpr_handle >> 32) as u32),

        )?;

        dev_dbg!(

            pdev.as_ref(),

            "SEC2 MBOX0: {:#x}, MBOX1{:#x}\n",

            mbox0,

            mbox1

        );



        if mbox0 != 0 {

            dev_err!(

                pdev.as_ref(),

                "Booter-load failed with error {:#x}\n",

                mbox0

            );

            return Err(ENODEV);

        }



        gsp_falcon.write_os_version(bar, gsp_fw.bootloader.app_version);



        // Poll for RISC-V to become active before running sequencer

        read_poll_timeout(

            || Ok(gsp_falcon.is_riscv_active(bar)),

            |val: &bool| *val,

            Delta::from_millis(10),

            Delta::from_secs(5),

        )?;



        dev_dbg!(

            pdev.as_ref(),

            "RISC-V active? {}\n",

            gsp_falcon.is_riscv_active(bar),

        );



        Ok(())

    }

}