Commit 5952d805 authored by Harish Chegondi's avatar Harish Chegondi Committed by Lucas De Marchi
Browse files

drm/xe/xe2hpg: Add Wa_18041344222 for Xe2_HPG 



Add Wa_18041344222 for Xe2_HPG that requires disabling
the perf mode for subslice count for eustall sampling
when the enabled slices are discontiguous.

Bspec: 79483, 56024
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: default avatarMatt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: default avatarHarish Chegondi <harish.chegondi@intel.com>
Reviewed-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Link: https://lore.kernel.org/r/b6a631a13a9fb7360e89d679e0797fae42d5a09e.1756855529.git.harish.chegondi@intel.com


Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
parent 6ee8adf1

drivers/gpu/drm/xe/regs/xe_gt_regs.h

+1 −0
Original line number Diff line number Diff line
@@ -522,6 +522,7 @@ 


#define TDL_CHICKEN				XE_REG_MCR(0xe5f4, XE_REG_OPTION_MASKED)

#define   QID_WAIT_FOR_THREAD_NOT_RUN_DISABLE	REG_BIT(12)

#define   EUSTALL_PERF_SAMPLING_DISABLE		REG_BIT(5)



#define LSC_CHICKEN_BIT_0			XE_REG_MCR(0xe7c8)

#define   DISABLE_D8_D16_COASLESCE		REG_BIT(30)

drivers/gpu/drm/xe/xe_gt_topology.c

+17 −0
Original line number Diff line number Diff line
@@ -12,6 +12,7 @@ 
#include "regs/xe_gt_regs.h"

#include "xe_assert.h"

#include "xe_gt.h"

#include "xe_gt_mcr.h"

#include "xe_gt_printk.h"

#include "xe_mmio.h"

#include "xe_wa.h"
@@ -328,3 +329,19 @@ bool xe_gt_has_compute_dss(struct xe_gt *gt, unsigned int dss) 
{

	return test_bit(dss, gt->fuse_topo.c_dss_mask);

}



bool xe_gt_has_discontiguous_dss_groups(const struct xe_gt *gt)

{

	unsigned int xecore;

	int last_group = -1;

	u16 group, instance;



	for_each_dss_steering(xecore, gt, group, instance) {

		if (last_group != group) {

			if (group - last_group > 1)

				return true;

			last_group = group;

		}

	}

	return false;

}

drivers/gpu/drm/xe/xe_gt_topology.h

+2 −0
Original line number Diff line number Diff line
@@ -47,4 +47,6 @@ xe_gt_topology_has_dss_in_quadrant(struct xe_gt *gt, int quad); 
bool xe_gt_has_geometry_dss(struct xe_gt *gt, unsigned int dss);

bool xe_gt_has_compute_dss(struct xe_gt *gt, unsigned int dss);



bool xe_gt_has_discontiguous_dss_groups(const struct xe_gt *gt);



#endif /* _XE_GT_TOPOLOGY_H_ */

drivers/gpu/drm/xe/xe_rtp.c

+6 −0
Original line number Diff line number Diff line
@@ -370,3 +370,9 @@ bool xe_rtp_match_psmi_enabled(const struct xe_gt *gt, 
{

	return xe_configfs_get_psmi_enabled(to_pci_dev(gt_to_xe(gt)->drm.dev));

}



bool xe_rtp_match_gt_has_discontiguous_dss_groups(const struct xe_gt *gt,

						  const struct xe_hw_engine *hwe)

{

	return xe_gt_has_discontiguous_dss_groups(gt);

}

drivers/gpu/drm/xe/xe_rtp.h

+3 −0
Original line number Diff line number Diff line
@@ -480,4 +480,7 @@ bool xe_rtp_match_not_sriov_vf(const struct xe_gt *gt, 
bool xe_rtp_match_psmi_enabled(const struct xe_gt *gt,

			       const struct xe_hw_engine *hwe);



bool xe_rtp_match_gt_has_discontiguous_dss_groups(const struct xe_gt *gt,

						  const struct xe_hw_engine *hwe);



#endif