Commit 59a266f0 authored by Ankit Nautiyal's avatar Ankit Nautiyal
Browse files

drm/i915/display: Store compressed bpp in U6.4 format 



DSC parameter bits_per_pixel is stored in U6.4 format.
The 4 bits represent the fractional part of the bpp.
Currently we use compressed_bpp member of dsc structure to store
only the integral part of the bits_per_pixel.
To store the full bits_per_pixel along with the fractional part,
compressed_bpp is changed to store bpp in U6.4 formats. Intergral
part is retrieved by simply right shifting the member compressed_bpp by 4.

v2:
-Use to_bpp_int, to_bpp_frac_dec, to_bpp_x16 helpers while dealing
 with compressed bpp. (Suraj)
-Fix comment styling. (Suraj)

v3:
-Add separate file for 6.4 fixed point helper(Jani, Nikula)
-Add comment for magic values(Suraj)

v4:
-Fix checkpatch warnings caused by renaming(Suraj)

v5:
-Rebase.
-Use existing helpers for conversion of bpp_int to bpp_x16
 and vice versa.

Signed-off-by: default avatarAnkit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: default avatarMitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: default avatarSuraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: default avatarSui Jingfeng <suijingfeng@loongson.cn>
Link: https://patchwork.freedesktop.org/patch/msgid/20231110101020.4067342-3-ankit.k.nautiyal@intel.com
parent 0c2287c9

drivers/gpu/drm/i915/display/icl_dsi.c

+5 −5
Original line number Diff line number Diff line
@@ -330,7 +330,7 @@ static int afe_clk(struct intel_encoder *encoder, 
	int bpp;



	if (crtc_state->dsc.compression_enable)

		bpp = crtc_state->dsc.compressed_bpp;

		bpp = to_bpp_int(crtc_state->dsc.compressed_bpp_x16);

	else

		bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
@@ -860,7 +860,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, 
	 * compressed and non-compressed bpp.

	 */

	if (crtc_state->dsc.compression_enable) {

		mul = crtc_state->dsc.compressed_bpp;

		mul = to_bpp_int(crtc_state->dsc.compressed_bpp_x16);

		div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);

	}
@@ -884,7 +884,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, 
		int bpp, line_time_us, byte_clk_period_ns;



		if (crtc_state->dsc.compression_enable)

			bpp = crtc_state->dsc.compressed_bpp;

			bpp = to_bpp_int(crtc_state->dsc.compressed_bpp_x16);

		else

			bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
@@ -1451,8 +1451,8 @@ static void gen11_dsi_get_timings(struct intel_encoder *encoder, 
	struct drm_display_mode *adjusted_mode =

					&pipe_config->hw.adjusted_mode;



	if (pipe_config->dsc.compressed_bpp) {

		int div = pipe_config->dsc.compressed_bpp;

	if (pipe_config->dsc.compressed_bpp_x16) {

		int div = to_bpp_int(pipe_config->dsc.compressed_bpp_x16);

		int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);



		adjusted_mode->crtc_htotal =

drivers/gpu/drm/i915/display/intel_audio.c

+1 −1
Original line number Diff line number Diff line
@@ -528,7 +528,7 @@ static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder, 
	h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay;

	h_total = crtc_state->hw.adjusted_mode.crtc_htotal;

	pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock;

	vdsc_bpp = crtc_state->dsc.compressed_bpp;

	vdsc_bpp = to_bpp_int(crtc_state->dsc.compressed_bpp_x16);

	cdclk = i915->display.cdclk.hw.cdclk;

	/* fec= 0.972261, using rounding multiplier of 1000000 */

	fec_coeff = 972261;

drivers/gpu/drm/i915/display/intel_bios.c

+2 −2
Original line number Diff line number Diff line
@@ -3414,8 +3414,8 @@ static void fill_dsc(struct intel_crtc_state *crtc_state, 


	crtc_state->pipe_bpp = bpc * 3;



	crtc_state->dsc.compressed_bpp = min(crtc_state->pipe_bpp,

					     VBT_DSC_MAX_BPP(dsc->max_bpp));

	crtc_state->dsc.compressed_bpp_x16 = to_bpp_x16(min(crtc_state->pipe_bpp,

							    VBT_DSC_MAX_BPP(dsc->max_bpp)));



	/*

	 * FIXME: This is ugly, and slice count should take DSC engine

drivers/gpu/drm/i915/display/intel_cdclk.c

+3 −2
Original line number Diff line number Diff line
@@ -2598,8 +2598,9 @@ static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state) 
		 * => CDCLK >= compressed_bpp * Pixel clock  / 2 * Bigjoiner Interface bits

		 */

		int bigjoiner_interface_bits = DISPLAY_VER(i915) > 13 ? 36 : 24;

		int min_cdclk_bj = (crtc_state->dsc.compressed_bpp * pixel_clock) /

				   (2 * bigjoiner_interface_bits);

		int min_cdclk_bj =

			(to_bpp_int_roundup(crtc_state->dsc.compressed_bpp_x16) *

			 pixel_clock) / (2 * bigjoiner_interface_bits);



		min_cdclk = max(min_cdclk, min_cdclk_bj);

	}

drivers/gpu/drm/i915/display/intel_display.c

+1 −1
Original line number Diff line number Diff line
@@ -5434,7 +5434,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, 


	PIPE_CONF_CHECK_I(dsc.compression_enable);

	PIPE_CONF_CHECK_I(dsc.dsc_split);

	PIPE_CONF_CHECK_I(dsc.compressed_bpp);

	PIPE_CONF_CHECK_I(dsc.compressed_bpp_x16);



	PIPE_CONF_CHECK_BOOL(splitter.enable);

	PIPE_CONF_CHECK_I(splitter.link_count);