Commit 59e9d9de authored by Hsiao Chien Sung's avatar Hsiao Chien Sung Committed by Chun-Kuang Hu
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drm/mediatek: Support "Pre-multiplied" blending in Mixer 



Support "Pre-multiplied" alpha blending mode in Mixer.
Before this patch, only the coverage mode is supported.

To replace the default setting that is set in mtk_ethdr_config(),
we change mtk_ddp_write_mask() to mtk_ddp_write(), and this change will
also reset the NON_PREMULTI_SOURCE bit that was assigned in
mtk_ethdr_config(). Therefore, we must still set NON_PREMULTI_SOURCE bit
if the blend mode is not DRM_MODE_BLEND_PREMULTI.

Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: default avatarHsiao Chien Sung <shawn.sung@mediatek.com>
Reviewed-by: default avatarCK Hu <ck.hu@mediatek.com>
Link: https://patchwork.kernel.org/project/dri-devel/patch/20240717-alpha-blending-v4-4-4b1c806c0749@mediatek.com/


Signed-off-by: default avatarChun-Kuang Hu <chunkuang.hu@kernel.org>
parent a3f7f7ef

drivers/gpu/drm/mediatek/mtk_ethdr.c

+7 −2
Original line number Diff line number Diff line
@@ -36,6 +36,7 @@ 
#define MIX_SRC_L0_EN				BIT(0)

#define MIX_L_SRC_CON(n)		(0x28 + 0x18 * (n))

#define NON_PREMULTI_SOURCE			(2 << 12)

#define PREMULTI_SOURCE				(3 << 12)

#define MIX_L_SRC_SIZE(n)		(0x30 + 0x18 * (n))

#define MIX_L_SRC_OFFSET(n)		(0x34 + 0x18 * (n))

#define MIX_FUNC_DCM0			0x120
@@ -176,6 +177,11 @@ void mtk_ethdr_layer_config(struct device *dev, unsigned int idx, 
		alpha_con |= state->base.alpha & MIXER_ALPHA;

	}



	if (state->base.pixel_blend_mode == DRM_MODE_BLEND_PREMULTI)

		alpha_con |= PREMULTI_SOURCE;

	else

		alpha_con |= NON_PREMULTI_SOURCE;



	if ((state->base.fb && !state->base.fb->format->has_alpha) ||

	    state->base.pixel_blend_mode == DRM_MODE_BLEND_PIXEL_NONE) {

		/*
@@ -193,8 +199,7 @@ void mtk_ethdr_layer_config(struct device *dev, unsigned int idx, 
	mtk_ddp_write(cmdq_pkt, pending->height << 16 | align_width, &mixer->cmdq_base,

		      mixer->regs, MIX_L_SRC_SIZE(idx));

	mtk_ddp_write(cmdq_pkt, offset, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_OFFSET(idx));

	mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_CON(idx),

			   0x1ff);

	mtk_ddp_write(cmdq_pkt, alpha_con, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_CON(idx));

	mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base, mixer->regs, MIX_SRC_CON,

			   BIT(idx));

}