Commit 59f6acb4 authored by Chunyan Zhang's avatar Chunyan Zhang Committed by Andrew Morton
Browse files

riscv: add RISC-V Svrsw60t59b extension support 

The Svrsw60t59b extension allows to free the PTE reserved bits 60 and 59
for software to use.

Link: https://lkml.kernel.org/r/20251113072806.795029-4-zhangchunyan@iscas.ac.cn


Signed-off-by: default avatarChunyan Zhang <zhangchunyan@iscas.ac.cn>
Reviewed-by: default avatarAlexandre Ghiti <alexghiti@rivosinc.com>
Reviewed-by: default avatarAndrew Jones <ajones@ventanamicro.com>
Reviewed-by: default avatarDeepak Gupta <debug@rivosinc.com>
Cc: Albert Ou <aou@eecs.berkeley.edu>
Cc: Alexandre Ghiti <alex@ghiti.fr>
Cc: Al Viro <viro@zeniv.linux.org.uk>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Axel Rasmussen <axelrasmussen@google.com>
Cc: Christian Brauner <brauner@kernel.org>
Cc: Conor Dooley <conor.dooley@microchip.com>
Cc: Conor Dooley <conor@kernel.org>
Cc: David Hildenbrand <david@redhat.com>
Cc: Jan Kara <jack@suse.cz>
Cc: Liam Howlett <liam.howlett@oracle.com>
Cc: Lorenzo Stoakes <lorenzo.stoakes@oracle.com>
Cc: Michal Hocko <mhocko@suse.com>
Cc: Mike Rapoport <rppt@kernel.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>
Cc: Peter Xu <peterx@redhat.com>
Cc: Rob Herring <robh@kernel.org>
Cc: Suren Baghdasaryan <surenb@google.com>
Cc: Vlastimil Babka <vbabka@suse.cz>
Cc: Yuanchu Xie <yuanchu@google.com>
Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
parent f59c0924

arch/riscv/Kconfig

+14 −0
Original line number Diff line number Diff line
@@ -849,6 +849,20 @@ config RISCV_ISA_ZICBOP 


	  If you don't know what to do here, say Y.



config RISCV_ISA_SVRSW60T59B

	bool "Svrsw60t59b extension support for using PTE bits 60 and 59"

	depends on MMU && 64BIT

	depends on RISCV_ALTERNATIVE

	default y

	help

	  Adds support to dynamically detect the presence of the Svrsw60t59b

	  extension and enable its usage.



	  The Svrsw60t59b extension allows to free the PTE reserved bits 60

	  and 59 for software to use.



	  If you don't know what to do here, say Y.



config TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI

	def_bool y

	# https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=aed44286efa8ae8717a77d94b51ac3614e2ca6dc

arch/riscv/include/asm/hwcap.h

+1 −0
Original line number Diff line number Diff line
@@ -106,6 +106,7 @@ 
#define RISCV_ISA_EXT_ZAAMO		97

#define RISCV_ISA_EXT_ZALRSC		98

#define RISCV_ISA_EXT_ZICBOP		99

#define RISCV_ISA_EXT_SVRSW60T59B	100



#define RISCV_ISA_EXT_XLINUXENVCFG	127

arch/riscv/kernel/cpufeature.c

+1 −0
Original line number Diff line number Diff line
@@ -539,6 +539,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { 
	__RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),

	__RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT),

	__RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),

	__RISCV_ISA_EXT_DATA(svrsw60t59b, RISCV_ISA_EXT_SVRSW60T59B),

	__RISCV_ISA_EXT_DATA(svvptc, RISCV_ISA_EXT_SVVPTC),

};