Unverified Commit 5a305d9d authored by Mark Brown's avatar Mark Brown
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ASoC: sun4i-spdif: Add 24bit support 

Merge series from codekipper@gmail.com:

I've tested this patch series on the Allwinner H3, A64, H6 and H313 SoCs
up to 192KHz.
24bit support is working on my H313 board but 16bit plays a bit slow and
I suspect that there is an issue with the clock setups. This is even
present without this patch stack. I would look to address this asap,
but for now can you please review what's here.
parents 8c695b4d 6e750d3e

sound/soc/sunxi/sun4i-spdif.c

+18 −6
Original line number Diff line number Diff line
@@ -176,6 +176,7 @@ struct sun4i_spdif_quirks { 
	unsigned int reg_dac_txdata;

	bool has_reset;

	unsigned int val_fctl_ftx;

	unsigned int mclk_multiplier;

};



struct sun4i_spdif_dev {
@@ -201,6 +202,10 @@ static void sun4i_spdif_configure(struct sun4i_spdif_dev *host) 
	regmap_update_bits(host->regmap, SUN4I_SPDIF_FCTL,

			   quirks->val_fctl_ftx, quirks->val_fctl_ftx);



	/* Valid data at the MSB of TXFIFO Register */

	regmap_update_bits(host->regmap, SUN4I_SPDIF_FCTL,

			   SUN4I_SPDIF_FCTL_TXIM, 0);



	/* clear TX counter */

	regmap_write(host->regmap, SUN4I_SPDIF_TXCNT, 0);

}
@@ -282,14 +287,17 @@ static int sun4i_spdif_hw_params(struct snd_pcm_substream *substream, 
		return -EINVAL;

	}



	host->dma_params_tx.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;

	switch (params_format(params)) {

	case SNDRV_PCM_FORMAT_S16_LE:

		fmt |= SUN4I_SPDIF_TXCFG_FMT16BIT;

		host->dma_params_tx.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;

		break;

	case SNDRV_PCM_FORMAT_S20_3LE:

		fmt |= SUN4I_SPDIF_TXCFG_FMT20BIT;

		break;

	case SNDRV_PCM_FORMAT_S24_LE:

	case SNDRV_PCM_FORMAT_S32_LE:

		fmt |= SUN4I_SPDIF_TXCFG_FMT24BIT;

		break;

	default:
@@ -313,6 +321,7 @@ static int sun4i_spdif_hw_params(struct snd_pcm_substream *substream, 
	default:

		return -EINVAL;

	}

	mclk *= host->quirks->mclk_multiplier;



	ret = clk_set_rate(host->spdif_clk, mclk);

	if (ret < 0) {
@@ -321,9 +330,6 @@ static int sun4i_spdif_hw_params(struct snd_pcm_substream *substream, 
		return ret;

	}



	regmap_update_bits(host->regmap, SUN4I_SPDIF_FCTL,

			   SUN4I_SPDIF_FCTL_TXIM, SUN4I_SPDIF_FCTL_TXIM);



	switch (rate) {

	case 22050:

	case 24000:
@@ -347,6 +353,7 @@ static int sun4i_spdif_hw_params(struct snd_pcm_substream *substream, 
	default:

		return -EINVAL;

	}

	mclk_div *= host->quirks->mclk_multiplier;



	reg_val = 0;

	reg_val |= SUN4I_SPDIF_TXCFG_ASS;
@@ -522,9 +529,10 @@ static const struct regmap_config sun4i_spdif_regmap_config = { 


#define SUN4I_RATES	SNDRV_PCM_RATE_8000_192000



#define SUN4I_FORMATS	(SNDRV_PCM_FORMAT_S16_LE | \

				SNDRV_PCM_FORMAT_S20_3LE | \

				SNDRV_PCM_FORMAT_S24_LE)

#define SUN4I_FORMATS	(SNDRV_PCM_FMTBIT_S16_LE | \

				SNDRV_PCM_FMTBIT_S20_3LE | \

				SNDRV_PCM_FMTBIT_S24_LE | \

				SNDRV_PCM_FMTBIT_S32_LE)



static struct snd_soc_dai_driver sun4i_spdif_dai = {

	.playback = {
@@ -540,24 +548,28 @@ static struct snd_soc_dai_driver sun4i_spdif_dai = { 
static const struct sun4i_spdif_quirks sun4i_a10_spdif_quirks = {

	.reg_dac_txdata	= SUN4I_SPDIF_TXFIFO,

	.val_fctl_ftx   = SUN4I_SPDIF_FCTL_FTX,

	.mclk_multiplier = 1,

};



static const struct sun4i_spdif_quirks sun6i_a31_spdif_quirks = {

	.reg_dac_txdata	= SUN4I_SPDIF_TXFIFO,

	.val_fctl_ftx   = SUN4I_SPDIF_FCTL_FTX,

	.has_reset	= true,

	.mclk_multiplier = 1,

};



static const struct sun4i_spdif_quirks sun8i_h3_spdif_quirks = {

	.reg_dac_txdata	= SUN8I_SPDIF_TXFIFO,

	.val_fctl_ftx   = SUN4I_SPDIF_FCTL_FTX,

	.has_reset	= true,

	.mclk_multiplier = 4,

};



static const struct sun4i_spdif_quirks sun50i_h6_spdif_quirks = {

	.reg_dac_txdata = SUN8I_SPDIF_TXFIFO,

	.val_fctl_ftx   = SUN50I_H6_SPDIF_FCTL_FTX,

	.has_reset      = true,

	.mclk_multiplier = 1,

};



static const struct of_device_id sun4i_spdif_of_match[] = {