Commit 5a364c2a authored by Vineet Gupta's avatar Vineet Gupta
Browse files

ARC: mm: PAE40 support 



This is the first working implementation of 40-bit physical address
extension on ARCv2.

Signed-off-by: default avatarAlexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: default avatarVineet Gupta <vgupta@synopsys.com>
parent 25d46418

arch/arc/Kconfig

+15 −0
Original line number Diff line number Diff line
@@ -453,6 +453,21 @@ config HIGHMEM 
	  kernel. Enable this to potentially allow access to rest of 2G and PAE

	  in future



config ARC_HAS_PAE40

	bool "Support for the 40-bit Physical Address Extension"

	default n

	depends on ISA_ARCV2

	select HIGHMEM

	help

	  Enable access to physical memory beyond 4G, only supported on

	  ARC cores with 40 bit Physical Addressing support



config ARCH_PHYS_ADDR_T_64BIT

	def_bool ARC_HAS_PAE40



config ARCH_DMA_ADDR_T_64BIT

	bool



config ARC_CURR_IN_REG

	bool "Dedicate Register r25 for current_task pointer"

	default y

arch/arc/include/asm/cache.h

+2 −0
Original line number Diff line number Diff line
@@ -65,6 +65,7 @@ extern int ioc_exists; 
#if defined(CONFIG_ARC_MMU_V3) || defined(CONFIG_ARC_MMU_V4)

#define ARC_REG_IC_PTAG		0x1E

#endif

#define ARC_REG_IC_PTAG_HI	0x1F



/* Bit val in IC_CTRL */

#define IC_CTRL_CACHE_DISABLE   0x1
@@ -77,6 +78,7 @@ extern int ioc_exists; 
#define ARC_REG_DC_FLSH		0x4B

#define ARC_REG_DC_FLDL		0x4C

#define ARC_REG_DC_PTAG		0x5C

#define ARC_REG_DC_PTAG_HI	0x5F



/* Bit val in DC_CTRL */

#define DC_CTRL_INV_MODE_FLUSH  0x40

arch/arc/include/asm/mmu.h

+7 −0
Original line number Diff line number Diff line
@@ -24,6 +24,7 @@ 
#if (CONFIG_ARC_MMU_VER < 4)

#define ARC_REG_TLBPD0		0x405

#define ARC_REG_TLBPD1		0x406

#define ARC_REG_TLBPD1HI	0	/* Dummy: allows code sharing with ARC700 */

#define ARC_REG_TLBINDEX	0x407

#define ARC_REG_TLBCOMMAND	0x408

#define ARC_REG_PID		0x409
@@ -31,6 +32,7 @@ 
#else

#define ARC_REG_TLBPD0		0x460

#define ARC_REG_TLBPD1		0x461

#define ARC_REG_TLBPD1HI	0x463

#define ARC_REG_TLBINDEX	0x464

#define ARC_REG_TLBCOMMAND	0x465

#define ARC_REG_PID		0x468
@@ -83,6 +85,11 @@ void arc_mmu_init(void); 
extern char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len);

void read_decode_mmu_bcr(void);



static inline int is_pae40_enabled(void)

{

	return IS_ENABLED(CONFIG_ARC_HAS_PAE40);

}



#endif	/* !__ASSEMBLY__ */



#endif

arch/arc/include/asm/page.h

+4 −0
Original line number Diff line number Diff line
@@ -56,7 +56,11 @@ typedef struct { 


#else /* !STRICT_MM_TYPECHECKS */



#ifdef CONFIG_ARC_HAS_PAE40

typedef unsigned long long pte_t;

#else

typedef unsigned long pte_t;

#endif

typedef unsigned long pgd_t;

typedef unsigned long pgprot_t;

arch/arc/include/asm/pgalloc.h

+3 −3
Original line number Diff line number Diff line
@@ -49,7 +49,7 @@ pmd_populate(struct mm_struct *mm, pmd_t *pmd, pgtable_t ptep) 


static inline int __get_order_pgd(void)

{

	return get_order(PTRS_PER_PGD * 4);

	return get_order(PTRS_PER_PGD * sizeof(pgd_t));

}



static inline pgd_t *pgd_alloc(struct mm_struct *mm)
@@ -87,7 +87,7 @@ static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd) 


static inline int __get_order_pte(void)

{

	return get_order(PTRS_PER_PTE * 4);

	return get_order(PTRS_PER_PTE * sizeof(pte_t));

}



static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
@@ -110,7 +110,7 @@ pte_alloc_one(struct mm_struct *mm, unsigned long address) 
	pte_pg = (pgtable_t)__get_free_pages(GFP_KERNEL | __GFP_REPEAT, __get_order_pte());

	if (!pte_pg)

		return 0;

	memzero((void *)pte_pg, PTRS_PER_PTE * 4);

	memzero((void *)pte_pg, PTRS_PER_PTE * sizeof(pte_t));

	page = virt_to_page(pte_pg);

	if (!pgtable_page_ctor(page)) {

		__free_page(page);