Commit 5a48d67a authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915/display: rename IS_DISPLAY_IP_STEP() to IS_DISPLAY_VER_STEP() 



Unify macro naming on VER.

Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Acked-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/6861e02f3adf15d56e89890000eb195070c33c9b.1724180287.git.jani.nikula@intel.com


Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
parent c8fc8346

drivers/gpu/drm/i915/display/intel_display_device.h

+3 −3
Original line number Diff line number Diff line
@@ -175,13 +175,13 @@ enum intel_display_subplatform { 
 * hardware fix is present and the software workaround is no longer necessary.

 * E.g.,

 *

 *    IS_DISPLAY_IP_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_B2)

 *    IS_DISPLAY_IP_STEP(i915, IP_VER(14, 0), STEP_C0, STEP_FOREVER)

 *    IS_DISPLAY_VER_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_B2)

 *    IS_DISPLAY_VER_STEP(i915, IP_VER(14, 0), STEP_C0, STEP_FOREVER)

 *

 * "STEP_FOREVER" can be passed as "until" for workarounds that have no upper

 * stepping bound for the specified IP version.

 */

#define IS_DISPLAY_IP_STEP(__i915, ipver, from, until) \

#define IS_DISPLAY_VER_STEP(__i915, ipver, from, until) \

	(IS_DISPLAY_VER_FULL((__i915), (ipver), (ipver)) && \

	 IS_DISPLAY_STEP((__i915), (from), (until)))

drivers/gpu/drm/i915/display/intel_fbc.c

+1 −1
Original line number Diff line number Diff line
@@ -1340,7 +1340,7 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state, 


	/* Wa_14016291713 */

	if ((IS_DISPLAY_VER(display, 12, 13) ||

	     IS_DISPLAY_IP_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_C0)) &&

	     IS_DISPLAY_VER_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_C0)) &&

	    crtc_state->has_psr && !crtc_state->has_panel_replay) {

		plane_state->no_fbc_reason = "PSR1 enabled (Wa_14016291713)";

		return 0;

drivers/gpu/drm/i915/display/intel_hdcp.c

+3 −3
Original line number Diff line number Diff line
@@ -42,11 +42,11 @@ intel_hdcp_disable_hdcp_line_rekeying(struct intel_encoder *encoder, 
		return;



	if (DISPLAY_VER(dev_priv) >= 14) {

		if (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_D0, STEP_FOREVER))

		if (IS_DISPLAY_VER_STEP(dev_priv, IP_VER(14, 0), STEP_D0, STEP_FOREVER))

			intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(hdcp->cpu_transcoder),

				     0, HDCP_LINE_REKEY_DISABLE);

		else if (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 1), STEP_B0, STEP_FOREVER) ||

			 IS_DISPLAY_IP_STEP(dev_priv, IP_VER(20, 0), STEP_B0, STEP_FOREVER))

		else if (IS_DISPLAY_VER_STEP(dev_priv, IP_VER(14, 1), STEP_B0, STEP_FOREVER) ||

			 IS_DISPLAY_VER_STEP(dev_priv, IP_VER(20, 0), STEP_B0, STEP_FOREVER))

			intel_de_rmw(dev_priv,

				     TRANS_DDI_FUNC_CTL(dev_priv, hdcp->cpu_transcoder),

				     0, TRANS_DDI_HDCP_LINE_REKEY_DISABLE);

drivers/gpu/drm/i915/display/intel_pmdemand.c

+1 −1
Original line number Diff line number Diff line
@@ -92,7 +92,7 @@ int intel_pmdemand_init(struct drm_i915_private *i915) 
				     &pmdemand_state->base,

				     &intel_pmdemand_funcs);



	if (IS_DISPLAY_IP_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_C0))

	if (IS_DISPLAY_VER_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_C0))

		/* Wa_14016740474 */

		intel_de_rmw(i915, XELPD_CHICKEN_DCPR_3, 0, DMD_RSP_TIMEOUT_DISABLE);

drivers/gpu/drm/i915/display/intel_psr.c

+4 −4
Original line number Diff line number Diff line
@@ -1868,14 +1868,14 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp, 
		 * cause issues if non-supported panels are used.

		 */

		if (!intel_dp->psr.panel_replay_enabled &&

		    (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0) ||

		    (IS_DISPLAY_VER_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0) ||

		     IS_ALDERLAKE_P(dev_priv)))

			intel_de_rmw(dev_priv, hsw_chicken_trans_reg(dev_priv, cpu_transcoder),

				     0, ADLP_1_BASED_X_GRANULARITY);



		/* Wa_16012604467:adlp,mtl[a0,b0] */

		if (!intel_dp->psr.panel_replay_enabled &&

		    IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0))

		    IS_DISPLAY_VER_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0))

			intel_de_rmw(dev_priv,

				     MTL_CLKGATE_DIS_TRANS(dev_priv, cpu_transcoder),

				     0,
@@ -2057,7 +2057,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp) 
	if (intel_dp->psr.sel_update_enabled) {

		/* Wa_16012604467:adlp,mtl[a0,b0] */

		if (!intel_dp->psr.panel_replay_enabled &&

		    IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0))

		    IS_DISPLAY_VER_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0))

			intel_de_rmw(dev_priv,

				     MTL_CLKGATE_DIS_TRANS(dev_priv, cpu_transcoder),

				     MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS, 0);
@@ -2542,7 +2542,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, 


	/* Wa_14014971492 */

	if (!crtc_state->has_panel_replay &&

	    ((IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0) ||

	    ((IS_DISPLAY_VER_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0) ||

	      IS_ALDERLAKE_P(dev_priv) || IS_TIGERLAKE(dev_priv))) &&

	    crtc_state->splitter.enable)

		crtc_state->psr2_su_area.y1 = 0;