Commit 5a50f2b6 authored by Rui Wang's avatar Rui Wang Committed by Hans Verkuil
Browse files

media: rkisp1: Fix filter mode register configuration 



The rkisp1_flt_config() function performs an initial direct write to
RKISP1_CIF_ISP_FILT_MODE without including the RKISP1_CIF_ISP_FLT_ENA
bit, which clears the filter enable bit in the hardware.

The subsequent read/modify/write sequence then reads back the register
with the enable bit already cleared and cannot restore it, resulting in
the filter being inadvertently disabled.

Remove the redundant direct write. The read/modify/write sequence alone
correctly preserves the existing enable bit state while updating the
DNR mode and filter configuration bits.

Signed-off-by: default avatarRui Wang <rui.wang@ideasonboard.com>
Reviewed-by: default avatarStefan Klug <stefan.klug@ideasonboard.com>
Reviewed-by: default avatarKieran Bingham <kieran.bingham@ideasonboard.com>
Reviewed-by: default avatarLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Link: https://patch.msgid.link/20260105171142.147792-2-rui.wang@ideasonboard.com


Signed-off-by: default avatarLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: default avatarHans Verkuil <hverkuil+cisco@kernel.org>
parent bb0365f4

drivers/media/platform/rockchip/rkisp1/rkisp1-params.c

+0 −6
Original line number Diff line number Diff line
@@ -411,12 +411,6 @@ static void rkisp1_flt_config(struct rkisp1_params *params, 
	rkisp1_write(params->rkisp1, RKISP1_CIF_ISP_FILT_LUM_WEIGHT,

		     arg->lum_weight);



	rkisp1_write(params->rkisp1, RKISP1_CIF_ISP_FILT_MODE,

		     (arg->mode ? RKISP1_CIF_ISP_FLT_MODE_DNR : 0) |

		     RKISP1_CIF_ISP_FLT_CHROMA_V_MODE(arg->chr_v_mode) |

		     RKISP1_CIF_ISP_FLT_CHROMA_H_MODE(arg->chr_h_mode) |

		     RKISP1_CIF_ISP_FLT_GREEN_STAGE1(arg->grn_stage1));



	/* avoid to override the old enable value */

	filt_mode = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_FILT_MODE);

	filt_mode &= RKISP1_CIF_ISP_FLT_ENA;