Commit 5a81ade1 authored by Lad Prabhakar's avatar Lad Prabhakar Committed by Geert Uytterhoeven
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ARM: dts: r8a7742: Add CAN support 



Add the definitions for can0 and can1 to the r8a7742 SoC dtsi.

Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: default avatarChris Paterson <Chris.Paterson2@renesas.com>
Link: https://lore.kernel.org/r/20200816190732.6905-4-prabhakar.mahadev-lad.rj@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 0c77ecdc

arch/arm/boot/dts/r8a7742.dtsi

+34 −0
Original line number Diff line number Diff line
@@ -36,6 +36,14 @@ audio_clk_c: audio_clk_c { 
		clock-frequency = <0>;

	};



	/* External CAN clock */

	can_clk: can {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		/* This value must be overridden by the board. */

		clock-frequency = <0>;

	};



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;
@@ -951,6 +959,32 @@ msiof3: spi@e6c90000 { 
			status = "disabled";

		};



		can0: can@e6e80000 {

			compatible = "renesas,can-r8a7742",

				     "renesas,rcar-gen2-can";

			reg = <0 0xe6e80000 0 0x1000>;

			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 916>,

				 <&cpg CPG_CORE R8A7742_CLK_RCAN>, <&can_clk>;

			clock-names = "clkp1", "clkp2", "can_clk";

			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;

			resets = <&cpg 916>;

			status = "disabled";

		};



		can1: can@e6e88000 {

			compatible = "renesas,can-r8a7742",

				     "renesas,rcar-gen2-can";

			reg = <0 0xe6e88000 0 0x1000>;

			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 915>,

				 <&cpg CPG_CORE R8A7742_CLK_RCAN>, <&can_clk>;

			clock-names = "clkp1", "clkp2", "can_clk";

			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;

			resets = <&cpg 915>;

			status = "disabled";

		};



		pwm0: pwm@e6e30000 {

			compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar";

			reg = <0 0xe6e30000 0 0x8>;