Commit 5a90bb21 authored Mar 13, 2026 by Roman Li Committed by Alex Deucher Mar 23, 2026

drm/amd/display: Clamp min DS DCFCLK value to DCN limit



[why & how]
DCN has a global limit for minimum DS DCFCLK during any operation.

Adhere to that limit and add a debug flag.

Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Signed-off-by: Ovidiu Bunea <ovidiu.bunea@amd.com>
Signed-off-by: Roman Li <roman.li@amd.com>
Signed-off-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

parent cb50faeb

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

+5 −0

Original line number	Diff line number	Diff line
		@@ -291,6 +291,11 @@ void dcn42_update_clocks(struct clk_mgr *clk_mgr_base,
		if (should_set_clock(safe_to_lower,
		new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
		clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;

		/* Clamp the requested clock to PMFW based on DCN limit. */
		if (dc->debug.min_deep_sleep_dcfclk_khz > 0 && clk_mgr_base->clks.dcfclk_deep_sleep_khz < dc->debug.min_deep_sleep_dcfclk_khz)
		clk_mgr_base->clks.dcfclk_deep_sleep_khz = dc->debug.min_deep_sleep_dcfclk_khz;

		dcn42_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz);
		}

drivers/gpu/drm/amd/display/dc/dc.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -1215,6 +1215,7 @@ struct dc_debug_options {
		bool enable_dmu_recovery;
		unsigned int force_vmin_threshold;
		bool enable_otg_frame_sync_pwa;
		unsigned int min_deep_sleep_dcfclk_khz;
		};

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

+1 −0

Original line number	Diff line number	Diff line
		@@ -760,6 +760,7 @@ static const struct dc_debug_options debug_defaults_drv = {
		.disable_z10 = false,
		.ignore_pg = true,
		.disable_stutter_for_wm_program = true,
		.min_deep_sleep_dcfclk_khz = 8000,
		};

		static const struct dc_check_config config_defaults = {