Commit 5aa09297 authored by Atish Patra's avatar Atish Patra Committed by Anup Patel
Browse files

RISC-V: KVM: Fix to allow hpmcounter31 from the guest 



The csr_fun defines a count parameter which defines the total number
CSRs emulated in KVM starting from the base. This value should be
equal to total number of counters possible for trap/emulation (32).

Fixes: a9ac6c37 ("RISC-V: KVM: Implement trap & emulate for hpmcounters")
Signed-off-by: default avatarAtish Patra <atishp@rivosinc.com>
Link: https://lore.kernel.org/r/20240816-kvm_pmu_fixes-v1-2-cdfce386dd93@rivosinc.com


Signed-off-by: default avatarAnup Patel <anup@brainfault.org>
parent 7d1ffc8b

arch/riscv/include/asm/kvm_vcpu_pmu.h

+3 −3
Original line number Diff line number Diff line
@@ -65,11 +65,11 @@ struct kvm_pmu { 


#if defined(CONFIG_32BIT)

#define KVM_RISCV_VCPU_HPMCOUNTER_CSR_FUNCS \

{.base = CSR_CYCLEH,	.count = 31,	.func = kvm_riscv_vcpu_pmu_read_hpm }, \

{.base = CSR_CYCLE,	.count = 31,	.func = kvm_riscv_vcpu_pmu_read_hpm },

{.base = CSR_CYCLEH,	.count = 32,	.func = kvm_riscv_vcpu_pmu_read_hpm }, \

{.base = CSR_CYCLE,	.count = 32,	.func = kvm_riscv_vcpu_pmu_read_hpm },

#else

#define KVM_RISCV_VCPU_HPMCOUNTER_CSR_FUNCS \

{.base = CSR_CYCLE,	.count = 31,	.func = kvm_riscv_vcpu_pmu_read_hpm },

{.base = CSR_CYCLE,	.count = 32,	.func = kvm_riscv_vcpu_pmu_read_hpm },

#endif



int kvm_riscv_vcpu_pmu_incr_fw(struct kvm_vcpu *vcpu, unsigned long fid);