Commit 5ab16198 authored by Yoshihiro Shimoda's avatar Yoshihiro Shimoda Committed by Geert Uytterhoeven
Browse files

clk: renesas: r8a779g0: Add PCIe clocks 



Add the PCIe module clocks, which are used by the PCIe modules on the
Renesas R-Car V4H (R8A779G0) SoC.  Note that the following descriptions
in the hardware manual Rev.0.81 about the PCIe module clocks are
incorrect:

    9.2.1.7 Software Reset Register 6 (SRCR6)
    9.2.1.12 Software Reset Register 11 (SRCR11)
    9.2.3.7 Module Stop Control Register 6 (MSTPCR6)

Please refer to Figures 104.3[ab] instead.

Signed-off-by: default avatarYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20231114122252.2266799-1-yoshihiro.shimoda.uh@renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent f154ef08

drivers/clk/renesas/r8a779g0-cpg-mssr.c

+2 −0
Original line number Diff line number Diff line
@@ -192,6 +192,8 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = { 
	DEF_MOD("msi3",		621,	R8A779G0_CLK_MSO),

	DEF_MOD("msi4",		622,	R8A779G0_CLK_MSO),

	DEF_MOD("msi5",		623,	R8A779G0_CLK_MSO),

	DEF_MOD("pciec0",	624,	R8A779G0_CLK_S0D2_HSC),

	DEF_MOD("pscie1",	625,	R8A779G0_CLK_S0D2_HSC),

	DEF_MOD("pwm",		628,	R8A779G0_CLK_SASYNCPERD4),

	DEF_MOD("rpc-if",	629,	R8A779G0_CLK_RPCD2),

	DEF_MOD("scif0",	702,	R8A779G0_CLK_SASYNCPERD4),