Commit 5ae8fb97 authored by Li Ma's avatar Li Ma Committed by Alex Deucher
Browse files

drm/amd/swsmu: enable Pstates profile levels for SMU v14.0.4 



Enables following UMD stable Pstates profile levels
of power_dpm_force_performance_level for SMU v14.0.4.

    - profile_peak
    - profile_min_mclk
    - profile_min_sclk
    - profile_standard

Signed-off-by: default avatarLi Ma <li.ma@amd.com>
Reviewed-by: default avatarTim Huang <tim.huang@amd.com>
Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 2fdc99b9

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

+15 −3
Original line number Diff line number Diff line
@@ -69,6 +69,9 @@ 
#define SMU_14_0_0_UMD_PSTATE_SOCCLK			678

#define SMU_14_0_0_UMD_PSTATE_FCLK			1800



#define SMU_14_0_4_UMD_PSTATE_GFXCLK			938

#define SMU_14_0_4_UMD_PSTATE_SOCCLK			938



#define FEATURE_MASK(feature) (1ULL << feature)

#define SMC_DPM_FEATURE ( \

	FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \
@@ -1296,6 +1299,9 @@ static int smu_v14_0_common_get_dpm_profile_freq(struct smu_context *smu, 
	switch (clk_type) {

	case SMU_GFXCLK:

	case SMU_SCLK:

		if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 4))

			clk_limit = SMU_14_0_4_UMD_PSTATE_GFXCLK;

		else

			clk_limit = SMU_14_0_0_UMD_PSTATE_GFXCLK;

		if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)

			smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &clk_limit);
@@ -1303,11 +1309,17 @@ static int smu_v14_0_common_get_dpm_profile_freq(struct smu_context *smu, 
			smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_SCLK, &clk_limit, NULL);

		break;

	case SMU_SOCCLK:

		if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 4))

			clk_limit = SMU_14_0_4_UMD_PSTATE_SOCCLK;

		else

			clk_limit = SMU_14_0_0_UMD_PSTATE_SOCCLK;

		if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)

			smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL, &clk_limit);

		break;

	case SMU_FCLK:

		if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 4))

			smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &clk_limit);

		else

			clk_limit = SMU_14_0_0_UMD_PSTATE_FCLK;

		if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)

			smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &clk_limit);