Commit 5aefaf11 authored by Sascha Bischoff's avatar Sascha Bischoff Committed by Marc Zyngier
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KVM: arm64: gic: Hide GICv5 for protected guests 



We don't support running protected guest with GICv5 at the moment.
Therefore, be sure that we don't expose it to the guest at all by
actively hiding it when running a protected guest.

Signed-off-by: default avatarSascha Bischoff <sascha.bischoff@arm.com>
Link: https://patch.msgid.link/20260319154937.3619520-34-sascha.bischoff@arm.com


Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
parent 7c31c06e

arch/arm64/include/asm/kvm_hyp.h

+1 −0
Original line number Diff line number Diff line
@@ -145,6 +145,7 @@ void __noreturn __host_enter(struct kvm_cpu_context *host_ctxt); 


extern u64 kvm_nvhe_sym(id_aa64pfr0_el1_sys_val);

extern u64 kvm_nvhe_sym(id_aa64pfr1_el1_sys_val);

extern u64 kvm_nvhe_sym(id_aa64pfr2_el1_sys_val);

extern u64 kvm_nvhe_sym(id_aa64isar0_el1_sys_val);

extern u64 kvm_nvhe_sym(id_aa64isar1_el1_sys_val);

extern u64 kvm_nvhe_sym(id_aa64isar2_el1_sys_val);

arch/arm64/kvm/arm.c

+1 −0
Original line number Diff line number Diff line
@@ -2530,6 +2530,7 @@ static void kvm_hyp_init_symbols(void) 
{

	kvm_nvhe_sym(id_aa64pfr0_el1_sys_val) = get_hyp_id_aa64pfr0_el1();

	kvm_nvhe_sym(id_aa64pfr1_el1_sys_val) = read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1);

	kvm_nvhe_sym(id_aa64pfr2_el1_sys_val) = read_sanitised_ftr_reg(SYS_ID_AA64PFR2_EL1);

	kvm_nvhe_sym(id_aa64isar0_el1_sys_val) = read_sanitised_ftr_reg(SYS_ID_AA64ISAR0_EL1);

	kvm_nvhe_sym(id_aa64isar1_el1_sys_val) = read_sanitised_ftr_reg(SYS_ID_AA64ISAR1_EL1);

	kvm_nvhe_sym(id_aa64isar2_el1_sys_val) = read_sanitised_ftr_reg(SYS_ID_AA64ISAR2_EL1);

arch/arm64/kvm/hyp/nvhe/sys_regs.c

+8 −0
Original line number Diff line number Diff line
@@ -20,6 +20,7 @@ 
 */

u64 id_aa64pfr0_el1_sys_val;

u64 id_aa64pfr1_el1_sys_val;

u64 id_aa64pfr2_el1_sys_val;

u64 id_aa64isar0_el1_sys_val;

u64 id_aa64isar1_el1_sys_val;

u64 id_aa64isar2_el1_sys_val;
@@ -108,6 +109,11 @@ static const struct pvm_ftr_bits pvmid_aa64pfr1[] = { 
	FEAT_END

};



static const struct pvm_ftr_bits pvmid_aa64pfr2[] = {

	MAX_FEAT(ID_AA64PFR2_EL1, GCIE, NI),

	FEAT_END

};



static const struct pvm_ftr_bits pvmid_aa64mmfr0[] = {

	MAX_FEAT_ENUM(ID_AA64MMFR0_EL1, PARANGE, 40),

	MAX_FEAT_ENUM(ID_AA64MMFR0_EL1, ASIDBITS, 16),
@@ -221,6 +227,8 @@ static u64 pvm_calc_id_reg(const struct kvm_vcpu *vcpu, u32 id) 
		return get_restricted_features(vcpu, id_aa64pfr0_el1_sys_val, pvmid_aa64pfr0);

	case SYS_ID_AA64PFR1_EL1:

		return get_restricted_features(vcpu, id_aa64pfr1_el1_sys_val, pvmid_aa64pfr1);

	case SYS_ID_AA64PFR2_EL1:

		return get_restricted_features(vcpu, id_aa64pfr2_el1_sys_val, pvmid_aa64pfr2);

	case SYS_ID_AA64ISAR0_EL1:

		return id_aa64isar0_el1_sys_val;

	case SYS_ID_AA64ISAR1_EL1: