Commit 5b40a508 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

PCI/ASPM: Avoid L0s and L1 on Freescale [1957:0451] Root Ports 



Christian reported that f3ac2ff1 ("PCI/ASPM: Enable all ClockPM and
ASPM states for devicetree platforms") broke booting on the A-EON X5000.

Override the L0s and L1 Support advertised in Link Capabilities by the
X5000 Root Ports ([1957:0451]) so we don't try to enable those states.

Fixes: f3ac2ff1 ("PCI/ASPM: Enable all ClockPM and ASPM states for devicetree platforms")
Fixes: df5192d9 ("PCI/ASPM: Enable only L0s and L1 for devicetree platforms")
Reported-by: default avatarChristian Zigotzky <chzigotzky@xenosoft.de>
Link: https://lore.kernel.org/r/db5c95a1-cf3e-46f9-8045-a1b04908051a@xenosoft.de


Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Tested-by: default avatarShawn Lin <shawn.lin@rock-chips.com>
Reviewed-by: default avatarLukas Wunner <lukas@wunner.de>
Link: https://patch.msgid.link/20251110222929.2140564-5-helgaas@kernel.org
parent 30579eeb

drivers/pci/quirks.c

+1 −0
Original line number Diff line number Diff line
@@ -2523,6 +2523,7 @@ static void quirk_disable_aspm_l0s_l1(struct pci_dev *dev) 
 * disable both L0s and L1 for now to be safe.

 */

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080, quirk_disable_aspm_l0s_l1);

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, 0x0451, quirk_disable_aspm_l0s_l1);



/*

 * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain