Commit 5b937a1e authored by Mikhail Paulyshka's avatar Mikhail Paulyshka Committed by Borislav Petkov (AMD)
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x86/rdrand: Disable RDSEED on AMD Cyan Skillfish 



AMD Cyan Skillfish (Family 17h, Model 47h, Stepping 0h) has an error that
causes RDSEED to always return 0xffffffff, while RDRAND works correctly.

Mask the RDSEED cap for this CPU so that both /proc/cpuinfo and direct CPUID
read report RDSEED as unavailable.

  [ bp: Move to amd.c, massage. ]

Signed-off-by: default avatarMikhail Paulyshka <me@mixaill.net>
Signed-off-by: default avatarBorislav Petkov (AMD) <bp@alien8.de>
Cc: <stable@kernel.org>
Link: https://lore.kernel.org/20250524145319.209075-1-me@mixaill.net
parent d7b8f8e2

arch/x86/include/asm/msr-index.h

+1 −0
Original line number Diff line number Diff line
@@ -628,6 +628,7 @@ 
#define MSR_AMD64_OSVW_STATUS		0xc0010141

#define MSR_AMD_PPIN_CTL		0xc00102f0

#define MSR_AMD_PPIN			0xc00102f1

#define MSR_AMD64_CPUID_FN_7		0xc0011002

#define MSR_AMD64_CPUID_FN_1		0xc0011004

#define MSR_AMD64_LS_CFG		0xc0011020

#define MSR_AMD64_DC_CFG		0xc0011022

arch/x86/kernel/cpu/amd.c

+7 −0
Original line number Diff line number Diff line
@@ -930,6 +930,13 @@ static void init_amd_zen2(struct cpuinfo_x86 *c) 
	init_spectral_chicken(c);

	fix_erratum_1386(c);

	zen2_zenbleed_check(c);



	/* Disable RDSEED on AMD Cyan Skillfish because of an error. */

	if (c->x86_model == 0x47 && c->x86_stepping == 0x0) {

		clear_cpu_cap(c, X86_FEATURE_RDSEED);

		msr_clear_bit(MSR_AMD64_CPUID_FN_7, 18);

		pr_emerg("RDSEED is not reliable on this platform; disabling.\n");

	}

}



static void init_amd_zen3(struct cpuinfo_x86 *c)

tools/arch/x86/include/asm/msr-index.h

+1 −0
Original line number Diff line number Diff line
@@ -628,6 +628,7 @@ 
#define MSR_AMD64_OSVW_STATUS		0xc0010141

#define MSR_AMD_PPIN_CTL		0xc00102f0

#define MSR_AMD_PPIN			0xc00102f1

#define MSR_AMD64_CPUID_FN_7		0xc0011002

#define MSR_AMD64_CPUID_FN_1		0xc0011004

#define MSR_AMD64_LS_CFG		0xc0011020

#define MSR_AMD64_DC_CFG		0xc0011022