Commit 5be50a8f authored by Kevin Wang's avatar Kevin Wang Committed by Alex Deucher
Browse files

drm/amdgpu: switch to use reg distance member for mmhub v1_7 



switch to use register distance member for mmhub v1_7
instead of hardcode

Signed-off-by: default avatarKevin Wang <kevin1.wang@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 4da999cd

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

+29 −15
Original line number Diff line number Diff line
@@ -56,15 +56,13 @@ static u64 mmhub_v1_7_get_fb_location(struct amdgpu_device *adev) 
void mmhub_v1_7_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,

				uint64_t page_table_base)

{

	/* two registers distance between regVM_CONTEXT0_* to regVM_CONTEXT1_* */

	int offset = regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32

			- regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;

	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];



	WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,

			offset * vmid, lower_32_bits(page_table_base));

			hub->ctx_addr_distance * vmid, lower_32_bits(page_table_base));



	WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,

			offset * vmid, upper_32_bits(page_table_base));

			hub->ctx_addr_distance * vmid, upper_32_bits(page_table_base));

}



static void mmhub_v1_7_init_gart_aperture_regs(struct amdgpu_device *adev)
@@ -222,6 +220,7 @@ static void mmhub_v1_7_disable_identity_aperture(struct amdgpu_device *adev) 


static void mmhub_v1_7_setup_vmid_config(struct amdgpu_device *adev)

{

	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];

	unsigned num_level, block_size;

	uint32_t tmp;

	int i;
@@ -260,25 +259,31 @@ static void mmhub_v1_7_setup_vmid_config(struct amdgpu_device *adev) 
		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

				    RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,

				    !amdgpu_noretry);

		WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_CNTL, i, tmp);

		WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0);

		WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0);

		WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, i*2,

		WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_CNTL,

				    i * hub->ctx_distance, tmp);

		WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,

				    i * hub->ctx_addr_distance, 0);

		WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,

				    i * hub->ctx_addr_distance, 0);

		WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,

				    i * hub->ctx_addr_distance,

				    lower_32_bits(adev->vm_manager.max_pfn - 1));

		WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, i*2,

		WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,

				    i * hub->ctx_addr_distance,

				    upper_32_bits(adev->vm_manager.max_pfn - 1));

	}

}



static void mmhub_v1_7_program_invalidation(struct amdgpu_device *adev)

{

	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];

	unsigned i;



	for (i = 0; i < 18; ++i) {

		WREG32_SOC15_OFFSET(MMHUB, 0, regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,

				    2 * i, 0xffffffff);

				    i * hub->eng_addr_distance, 0xffffffff);

		WREG32_SOC15_OFFSET(MMHUB, 0, regVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,

				    2 * i, 0x1f);

				    i * hub->eng_addr_distance, 0x1f);

	}

}
@@ -312,12 +317,14 @@ static int mmhub_v1_7_gart_enable(struct amdgpu_device *adev) 


static void mmhub_v1_7_gart_disable(struct amdgpu_device *adev)

{

	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];

	u32 tmp;

	u32 i;



	/* Disable all tables */

	for (i = 0; i < 16; i++)

		WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT0_CNTL, i, 0);

		WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT0_CNTL,

				    i * hub->ctx_distance, 0);



	/* Setup TLB control */

	tmp = RREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL);
@@ -406,6 +413,13 @@ static void mmhub_v1_7_init(struct amdgpu_device *adev) 
	hub->vm_l2_pro_fault_cntl =

		SOC15_REG_OFFSET(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL);



	hub->ctx_distance = regVM_CONTEXT1_CNTL - regVM_CONTEXT0_CNTL;

	hub->ctx_addr_distance = regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -

		regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;

	hub->eng_distance = regVM_INVALIDATE_ENG1_REQ - regVM_INVALIDATE_ENG0_REQ;

	hub->eng_addr_distance = regVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -

		regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;



}



static void mmhub_v1_7_update_medium_grain_clock_gating(struct amdgpu_device *adev,