Commit 5c00eca9 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'x86_urgent_for_v6.16_rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 fixes from Borislav Petkov:

 - Make sure the array tracking which kernel text positions need to be
   alternatives-patched doesn't get mishandled by out-of-order
   modifications, leading to it overflowing and causing page faults when
   patching

 - Avoid an infinite loop when early code does a ranged TLB invalidation
   before the broadcast TLB invalidation count of how many pages it can
   flush, has been read from CPUID

 - Fix a CONFIG_MODULES typo

 - Disable broadcast TLB invalidation when PTI is enabled to avoid an
   overflow of the bitmap tracking dynamic ASIDs which need to be
   flushed when the kernel switches between the user and kernel address
   space

 - Handle the case of a CPU going offline and thus reporting zeroes when
   reading top-level events in the resctrl code

* tag 'x86_urgent_for_v6.16_rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/alternatives: Fix int3 handling failure from broken text_poke array
  x86/mm: Fix early boot use of INVPLGB
  x86/its: Fix an ifdef typo in its_alloc()
  x86/mm: Disable INVLPGB when PTI is enabled
  x86,fs/resctrl: Remove inappropriate references to cacheinfo in the resctrl subsystem
parents 33efa7db 2aebf5ee

arch/x86/kernel/alternative.c

+2 −2
Original line number Diff line number Diff line
@@ -228,7 +228,7 @@ static void *its_alloc(void) 
	struct its_array *pages = &its_pages;

	void *page;



#ifdef CONFIG_MODULE

#ifdef CONFIG_MODULES

	if (its_mod)

		pages = &its_mod->arch.its_pages;

#endif
@@ -3138,6 +3138,6 @@ void __ref smp_text_poke_batch_add(void *addr, const void *opcode, size_t len, c 
 */

void __ref smp_text_poke_single(void *addr, const void *opcode, size_t len, const void *emulate)

{

	__smp_text_poke_batch_add(addr, opcode, len, emulate);

	smp_text_poke_batch_add(addr, opcode, len, emulate);

	smp_text_poke_batch_finish();

}

arch/x86/kernel/cpu/amd.c

+1 −1
Original line number Diff line number Diff line
@@ -31,7 +31,7 @@ 


#include "cpu.h"



u16 invlpgb_count_max __ro_after_init;

u16 invlpgb_count_max __ro_after_init = 1;



static inline int rdmsrq_amd_safe(unsigned msr, u64 *p)

{

arch/x86/kernel/cpu/resctrl/core.c

+4 −2
Original line number Diff line number Diff line
@@ -498,6 +498,7 @@ static void domain_add_cpu_mon(int cpu, struct rdt_resource *r) 
	struct rdt_hw_mon_domain *hw_dom;

	struct rdt_domain_hdr *hdr;

	struct rdt_mon_domain *d;

	struct cacheinfo *ci;

	int err;



	lockdep_assert_held(&domain_list_lock);
@@ -525,12 +526,13 @@ static void domain_add_cpu_mon(int cpu, struct rdt_resource *r) 
	d = &hw_dom->d_resctrl;

	d->hdr.id = id;

	d->hdr.type = RESCTRL_MON_DOMAIN;

	d->ci = get_cpu_cacheinfo_level(cpu, RESCTRL_L3_CACHE);

	if (!d->ci) {

	ci = get_cpu_cacheinfo_level(cpu, RESCTRL_L3_CACHE);

	if (!ci) {

		pr_warn_once("Can't find L3 cache for CPU:%d resource %s\n", cpu, r->name);

		mon_domain_free(hw_dom);

		return;

	}

	d->ci_id = ci->id;

	cpumask_set_cpu(cpu, &d->hdr.cpu_mask);



	arch_mon_domain_online(r, d);

arch/x86/mm/pti.c

+5 −0
Original line number Diff line number Diff line
@@ -98,6 +98,11 @@ void __init pti_check_boottime_disable(void) 
		return;



	setup_force_cpu_cap(X86_FEATURE_PTI);



	if (cpu_feature_enabled(X86_FEATURE_INVLPGB)) {

		pr_debug("PTI enabled, disabling INVLPGB\n");

		setup_clear_cpu_cap(X86_FEATURE_INVLPGB);

	}

}



static int __init pti_parse_cmdline(char *arg)

fs/resctrl/ctrlmondata.c

+9 −4
Original line number Diff line number Diff line
@@ -594,9 +594,10 @@ int rdtgroup_mondata_show(struct seq_file *m, void *arg) 
	struct rmid_read rr = {0};

	struct rdt_mon_domain *d;

	struct rdtgroup *rdtgrp;

	int domid, cpu, ret = 0;

	struct rdt_resource *r;

	struct cacheinfo *ci;

	struct mon_data *md;

	int domid, ret = 0;



	rdtgrp = rdtgroup_kn_lock_live(of->kn);

	if (!rdtgrp) {
@@ -623,10 +624,14 @@ int rdtgroup_mondata_show(struct seq_file *m, void *arg) 
		 * one that matches this cache id.

		 */

		list_for_each_entry(d, &r->mon_domains, hdr.list) {

			if (d->ci->id == domid) {

				rr.ci = d->ci;

			if (d->ci_id == domid) {

				rr.ci_id = d->ci_id;

				cpu = cpumask_any(&d->hdr.cpu_mask);

				ci = get_cpu_cacheinfo_level(cpu, RESCTRL_L3_CACHE);

				if (!ci)

					continue;

				mon_event_read(&rr, r, NULL, rdtgrp,

					       &d->ci->shared_cpu_map, evtid, false);

					       &ci->shared_cpu_map, evtid, false);

				goto checkresult;

			}

		}