Commit 5c03e584 authored by Feifei Xu's avatar Feifei Xu Committed by Alex Deucher
Browse files

drm/amdgpu:add smu mode1/2 support for aldebaran 



Use MSG_GfxDriverReset for mode reset and retire MSG_Mode1Reset.
Centralize soc15_asic_mode1_reset() and nv_asic_mode1_reset()functions.
Add mode2_reset_is_support() for smu->ppt_funcs.

Signed-off-by: default avatarFeifei Xu <Feifei.Xu@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 4c2e5f51

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+1 −0
Original line number Diff line number Diff line
@@ -1261,6 +1261,7 @@ void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 
					     const u32 array_size);



bool amdgpu_device_supports_atpx(struct drm_device *dev);

int amdgpu_device_mode1_reset(struct amdgpu_device *adev);

bool amdgpu_device_supports_boco(struct drm_device *dev);

bool amdgpu_device_supports_baco(struct drm_device *dev);

bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+39 −0
Original line number Diff line number Diff line
@@ -4248,6 +4248,45 @@ bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev) 
		return false;

}



int amdgpu_device_mode1_reset(struct amdgpu_device *adev)

{

        u32 i;

        int ret = 0;



        amdgpu_atombios_scratch_regs_engine_hung(adev, true);



        dev_info(adev->dev, "GPU mode1 reset\n");



        /* disable BM */

        pci_clear_master(adev->pdev);



        amdgpu_device_cache_pci_state(adev->pdev);



        if (amdgpu_dpm_is_mode1_reset_supported(adev)) {

                dev_info(adev->dev, "GPU smu mode1 reset\n");

                ret = amdgpu_dpm_mode1_reset(adev);

        } else {

                dev_info(adev->dev, "GPU psp mode1 reset\n");

                ret = psp_gpu_reset(adev);

        }



        if (ret)

                dev_err(adev->dev, "GPU mode1 reset failed\n");



        amdgpu_device_load_pci_state(adev->pdev);



        /* wait for asic to come out of reset */

        for (i = 0; i < adev->usec_timeout; i++) {

                u32 memsize = adev->nbio.funcs->get_memsize(adev);



                if (memsize != 0xffffffff)

                        break;

                udelay(1);

        }



        amdgpu_atombios_scratch_regs_engine_hung(adev, false);

        return ret;

}



static int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,

					struct amdgpu_job *job,

drivers/gpu/drm/amd/amdgpu/nv.c

+1 −39
Original line number Diff line number Diff line
@@ -484,44 +484,6 @@ static int nv_read_register(struct amdgpu_device *adev, u32 se_num, 
	return -EINVAL;

}



static int nv_asic_mode1_reset(struct amdgpu_device *adev)

{

	u32 i;

	int ret = 0;



	amdgpu_atombios_scratch_regs_engine_hung(adev, true);



	/* disable BM */

	pci_clear_master(adev->pdev);



	amdgpu_device_cache_pci_state(adev->pdev);



	if (amdgpu_dpm_is_mode1_reset_supported(adev)) {

		dev_info(adev->dev, "GPU smu mode1 reset\n");

		ret = amdgpu_dpm_mode1_reset(adev);

	} else {

		dev_info(adev->dev, "GPU psp mode1 reset\n");

		ret = psp_gpu_reset(adev);

	}



	if (ret)

		dev_err(adev->dev, "GPU mode1 reset failed\n");

	amdgpu_device_load_pci_state(adev->pdev);



	/* wait for asic to come out of reset */

	for (i = 0; i < adev->usec_timeout; i++) {

		u32 memsize = adev->nbio.funcs->get_memsize(adev);



		if (memsize != 0xffffffff)

			break;

		udelay(1);

	}



	amdgpu_atombios_scratch_regs_engine_hung(adev, false);



	return ret;

}



static int nv_asic_mode2_reset(struct amdgpu_device *adev)

{

	u32 i;
@@ -624,7 +586,7 @@ static int nv_asic_reset(struct amdgpu_device *adev) 
		break;

	default:

		dev_info(adev->dev, "MODE1 reset\n");

		ret = nv_asic_mode1_reset(adev);

		ret = amdgpu_device_mode1_reset(adev);

		break;

	}

drivers/gpu/drm/amd/amdgpu/soc15.c

+19 −37
Original line number Diff line number Diff line
@@ -650,40 +650,6 @@ void soc15_program_register_sequence(struct amdgpu_device *adev, 


}



static int soc15_asic_mode1_reset(struct amdgpu_device *adev)

{

	u32 i;

	int ret = 0;



	amdgpu_atombios_scratch_regs_engine_hung(adev, true);



	dev_info(adev->dev, "GPU mode1 reset\n");



	/* disable BM */

	pci_clear_master(adev->pdev);



	amdgpu_device_cache_pci_state(adev->pdev);



	ret = psp_gpu_reset(adev);

	if (ret)

		dev_err(adev->dev, "GPU mode1 reset failed\n");



	amdgpu_device_load_pci_state(adev->pdev);



	/* wait for asic to come out of reset */

	for (i = 0; i < adev->usec_timeout; i++) {

		u32 memsize = adev->nbio.funcs->get_memsize(adev);



		if (memsize != 0xffffffff)

			break;

		udelay(1);

	}



	amdgpu_atombios_scratch_regs_engine_hung(adev, false);



	return ret;

}



static int soc15_asic_baco_reset(struct amdgpu_device *adev)

{

	struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
@@ -708,13 +674,21 @@ static enum amd_reset_method 
soc15_asic_reset_method(struct amdgpu_device *adev)

{

	bool baco_reset = false;

	bool connected_to_cpu = false;

	struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);



        if (adev->gmc.xgmi.supported && adev->gmc.xgmi.connected_to_cpu)

                connected_to_cpu = true;



	if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||

	    amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||

	    amdgpu_reset_method == AMD_RESET_METHOD_BACO ||

	    amdgpu_reset_method == AMD_RESET_METHOD_PCI)

	    amdgpu_reset_method == AMD_RESET_METHOD_PCI) {

		/* If connected to cpu, driver only support mode2 */

                if (connected_to_cpu)

                        return AMD_RESET_METHOD_MODE2;

                return amdgpu_reset_method;

        }



	if (amdgpu_reset_method != -1)

		dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
@@ -740,6 +714,14 @@ soc15_asic_reset_method(struct amdgpu_device *adev) 
		if ((ras && ras->supported) && adev->pm.fw_version <= 0x283400)

			baco_reset = false;

		break;

	case CHIP_ALDEBARAN:

		 /*

		 * 1.connected to cpu: driver issue mode2 reset

		 * 2.discret gpu: driver issue mode1 reset

		 */

		if (connected_to_cpu)

			return AMD_RESET_METHOD_MODE2;

		break;

	default:

		break;

	}
@@ -769,7 +751,7 @@ static int soc15_asic_reset(struct amdgpu_device *adev) 
		return amdgpu_dpm_mode2_reset(adev);

	default:

		dev_info(adev->dev, "MODE1 reset\n");

		return soc15_asic_mode1_reset(adev);

		return amdgpu_device_mode1_reset(adev);

	}

}

drivers/gpu/drm/amd/pm/inc/aldebaran_ppsmc.h

+21 −4
Original line number Diff line number Diff line
@@ -36,7 +36,7 @@ 
// Message Definitions:

#define PPSMC_MSG_TestMessage                    0x1

#define PPSMC_MSG_GetSmuVersion                  0x2

#define PPSMC_MSG_Mode1Reset                     0x3

#define PPSMC_MSG_GfxDriverReset                 0x3

#define PPSMC_MSG_GetDriverIfVersion             0x4

#define PPSMC_MSG_spare1                         0x5

#define PPSMC_MSG_spare2                         0x6
@@ -70,8 +70,8 @@ 
#define PPSMC_MSG_SetPptLimit                    0x22

#define PPSMC_MSG_GetPptLimit                    0x23

#define PPSMC_MSG_PrepareMp1ForUnload            0x24

#define PPSMC_MSG_PrepareMp1ForReset             0x25

#define PPSMC_MSG_SoftReset                      0x26

#define PPSMC_MSG_PrepareMp1ForReset             0x25 //retired in 68.07

#define PPSMC_MSG_SoftReset                      0x26 //retired in 68.07

#define PPSMC_MSG_RunDcBtc                       0x27

#define PPSMC_MSG_DramLogSetDramAddrHigh         0x28

#define PPSMC_MSG_DramLogSetDramAddrLow          0x29
@@ -92,7 +92,24 @@ 
#define PPSMC_MSG_DisableDeterminism             0x3A

#define PPSMC_MSG_SetUclkDpmMode                 0x3B



#define PPSMC_Message_Count                      0x3C

//STB to dram log

#define PPSMC_MSG_DumpSTBtoDram                     0x3C

#define PPSMC_MSG_STBtoDramLogSetDramAddrHigh       0x3D

#define PPSMC_MSG_STBtoDramLogSetDramAddrLow        0x3E

#define PPSMC_MSG_STBtoDramLogSetDramSize           0x3F

#define PPSMC_MSG_SetSystemVirtualSTBtoDramAddrHigh 0x40

#define PPSMC_MSG_SetSystemVirtualSTBtoDramAddrLow  0x41



#define PPSMC_Message_Count                      0x42



//PPSMC Reset Types

#define PPSMC_RESET_TYPE_WARM_RESET              0x00

#define PPSMC_RESET_TYPE_DRIVER_MODE_1_RESET     0x01 //driver msg argument should be 1 for mode-1

#define PPSMC_RESET_TYPE_DRIVER_MODE_2_RESET     0x02 //and 2 for mode-2

#define PPSMC_RESET_TYPE_PCIE_LINK_RESET         0x03

#define PPSMC_RESET_TYPE_BIF_LINK_RESET          0x04

#define PPSMC_RESET_TYPE_PF0_FLR_RESET           0x05





typedef enum {

  GFXOFF_ERROR_NO_ERROR,