Commit 5c30cfa2 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915/dmc: Convert DMC code to intel_display 



struct intel_display will replace struct drm_i915_private as
the main thing for display code. Convert the DMC code to
use it (as much as possible at this stage).

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240906143306.15937-7-ville.syrjala@linux.intel.com


Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
parent e9a11477

drivers/gpu/drm/i915/display/intel_display.c

+4 −3
Original line number Diff line number Diff line
@@ -1690,7 +1690,7 @@ static void hsw_crtc_enable(struct intel_atomic_state *state, 


	for_each_intel_crtc_in_pipe_mask_reverse(&dev_priv->drm, pipe_crtc,

						 intel_crtc_joined_pipe_mask(new_crtc_state))

		intel_dmc_enable_pipe(dev_priv, pipe_crtc->pipe);

		intel_dmc_enable_pipe(display, pipe_crtc->pipe);



	intel_encoders_pre_pll_enable(state, crtc);
@@ -1843,9 +1843,10 @@ static void ilk_crtc_disable(struct intel_atomic_state *state, 
static void hsw_crtc_disable(struct intel_atomic_state *state,

			     struct intel_crtc *crtc)

{

	struct intel_display *display = to_intel_display(state);

	struct drm_i915_private *i915 = to_i915(display->drm);

	const struct intel_crtc_state *old_crtc_state =

		intel_atomic_get_old_crtc_state(state, crtc);

	struct drm_i915_private *i915 = to_i915(crtc->base.dev);

	struct intel_crtc *pipe_crtc;



	/*
@@ -1867,7 +1868,7 @@ static void hsw_crtc_disable(struct intel_atomic_state *state, 


	for_each_intel_crtc_in_pipe_mask(&i915->drm, pipe_crtc,

					 intel_crtc_joined_pipe_mask(old_crtc_state))

		intel_dmc_disable_pipe(i915, pipe_crtc->pipe);

		intel_dmc_disable_pipe(display, pipe_crtc->pipe);

}



static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display_debugfs.c

+1 −1
Original line number Diff line number Diff line
@@ -1069,7 +1069,7 @@ void intel_display_debugfs_register(struct drm_i915_private *i915) 


	intel_bios_debugfs_register(display);

	intel_cdclk_debugfs_register(display);

	intel_dmc_debugfs_register(i915);

	intel_dmc_debugfs_register(display);

	intel_fbc_debugfs_register(display);

	intel_hpd_debugfs_register(i915);

	intel_opregion_debugfs_register(display);

drivers/gpu/drm/i915/display/intel_display_driver.c

+3 −3
Original line number Diff line number Diff line
@@ -237,7 +237,7 @@ int intel_display_driver_probe_noirq(struct drm_i915_private *i915) 
	if (!HAS_DISPLAY(i915))

		return 0;



	intel_dmc_init(i915);

	intel_dmc_init(display);



	i915->display.wq.modeset = alloc_ordered_workqueue("i915_modeset", 0);

	i915->display.wq.flip = alloc_workqueue("i915_flip", WQ_HIGHPRI |
@@ -272,7 +272,7 @@ int intel_display_driver_probe_noirq(struct drm_i915_private *i915) 
	return 0;



cleanup_vga_client_pw_domain_dmc:

	intel_dmc_fini(i915);

	intel_dmc_fini(display);

	intel_power_domains_driver_remove(i915);

cleanup_vga:

	intel_vga_unregister(display);
@@ -621,7 +621,7 @@ void intel_display_driver_remove_nogem(struct drm_i915_private *i915) 
{

	struct intel_display *display = &i915->display;



	intel_dmc_fini(i915);

	intel_dmc_fini(display);



	intel_power_domains_driver_remove(i915);

drivers/gpu/drm/i915/display/intel_display_power.c

+9 −8
Original line number Diff line number Diff line
@@ -1445,7 +1445,7 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv, 
	gen9_dbuf_enable(dev_priv);



	if (resume)

		intel_dmc_load_program(dev_priv);

		intel_dmc_load_program(display);

}



static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
@@ -1515,7 +1515,7 @@ static void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume 
	gen9_dbuf_enable(dev_priv);



	if (resume)

		intel_dmc_load_program(dev_priv);

		intel_dmc_load_program(display);

}



static void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
@@ -1687,7 +1687,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv, 
		intel_de_rmw(dev_priv, CHICKEN_MISC_2, BMG_DARB_HALF_BLK_END_BURST, 1);



	if (resume)

		intel_dmc_load_program(dev_priv);

		intel_dmc_load_program(display);



	/* Wa_14011508470:tgl,dg1,rkl,adl-s,adl-p,dg2 */

	if (IS_DISPLAY_VER_FULL(dev_priv, IP_VER(12, 0), IP_VER(13, 0)))
@@ -1718,7 +1718,7 @@ static void icl_display_core_uninit(struct drm_i915_private *dev_priv) 
		return;



	gen9_disable_dc_states(display);

	intel_dmc_disable_program(dev_priv);

	intel_dmc_disable_program(display);



	/* 1. Disable all display engine functions -> aready done */
@@ -2073,7 +2073,8 @@ void intel_power_domains_disable(struct drm_i915_private *i915) 
 */

void intel_power_domains_suspend(struct drm_i915_private *i915, bool s2idle)

{

	struct i915_power_domains *power_domains = &i915->display.power.domains;

	struct intel_display *display = &i915->display;

	struct i915_power_domains *power_domains = &display->power.domains;

	intel_wakeref_t wakeref __maybe_unused =

		fetch_and_zero(&power_domains->init_wakeref);
@@ -2087,7 +2088,7 @@ void intel_power_domains_suspend(struct drm_i915_private *i915, bool s2idle) 
	 * that would be blocked if the firmware was inactive.

	 */

	if (!(power_domains->allowed_dc_mask & DC_STATE_EN_DC9) && s2idle &&

	    intel_dmc_has_payload(i915)) {

	    intel_dmc_has_payload(display)) {

		intel_display_power_flush_work(i915);

		intel_power_domains_verify_state(i915);

		return;
@@ -2286,7 +2287,7 @@ void intel_display_power_resume(struct drm_i915_private *i915) 
	if (DISPLAY_VER(i915) >= 11) {

		bxt_disable_dc9(display);

		icl_display_core_init(i915, true);

		if (intel_dmc_has_payload(i915)) {

		if (intel_dmc_has_payload(display)) {

			if (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC6)

				skl_enable_dc6(display);

			else if (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC5)
@@ -2295,7 +2296,7 @@ void intel_display_power_resume(struct drm_i915_private *i915) 
	} else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {

		bxt_disable_dc9(display);

		bxt_display_core_init(i915, true);

		if (intel_dmc_has_payload(i915) &&

		if (intel_dmc_has_payload(display) &&

		    (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC5))

			gen9_enable_dc5(display);

	} else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {

drivers/gpu/drm/i915/display/intel_display_power_well.c

+3 −5
Original line number Diff line number Diff line
@@ -817,7 +817,7 @@ static void assert_can_enable_dc5(struct intel_display *display) 
		      "DC5 already programmed to be enabled.\n");

	assert_rpm_wakelock_held(&dev_priv->runtime_pm);



	assert_dmc_loaded(dev_priv);

	assert_dmc_loaded(display);

}



void gen9_enable_dc5(struct intel_display *display)
@@ -840,8 +840,6 @@ void gen9_enable_dc5(struct intel_display *display) 


static void assert_can_enable_dc6(struct intel_display *display)

{

	struct drm_i915_private *dev_priv = to_i915(display->drm);



	drm_WARN_ONCE(display->drm,

		      (intel_de_read(display, UTIL_PIN_CTL) &

		       (UTIL_PIN_ENABLE | UTIL_PIN_MODE_MASK)) ==
@@ -852,7 +850,7 @@ static void assert_can_enable_dc6(struct intel_display *display) 
		       DC_STATE_EN_UPTO_DC6),

		      "DC6 already programmed to be enabled.\n");



	assert_dmc_loaded(dev_priv);

	assert_dmc_loaded(display);

}



void skl_enable_dc6(struct intel_display *display)
@@ -1031,7 +1029,7 @@ static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv, 
	struct intel_display *display = &dev_priv->display;

	struct i915_power_domains *power_domains = &display->power.domains;



	if (!intel_dmc_has_payload(dev_priv))

	if (!intel_dmc_has_payload(display))

		return;



	switch (power_domains->target_dc_state) {