dt-bindings: display: samsung,exynos7-decon: convert to dtschema

Device-Tree bindings for Samsung Exynos7 SoC display controller (DECON)

DECON (Display and Enhancement Controller) is the Display Controller for the

Exynos7 series of SoCs which transfers the image data from a video memory

buffer to an external LCD interface.

Required properties:

- compatible: value should be "samsung,exynos7-decon";

- reg: physical base address and length of the DECON registers set.

- interrupts: should contain a list of all DECON IP block interrupts in the

		 order: FIFO Level, VSYNC, LCD_SYSTEM. The interrupt specifier

		 format depends on the interrupt controller used.

- interrupt-names: should contain the interrupt names: "fifo", "vsync",

	"lcd_sys", in the same order as they were listed in the interrupts

        property.

- pinctrl-0: pin control group to be used for this controller.

- pinctrl-names: must contain a "default" entry.

- clocks: must include clock specifiers corresponding to entries in the

         clock-names property.

- clock-names: list of clock names sorted in the same order as the clocks

               property. Must contain "pclk_decon0", "aclk_decon0",

	       "decon0_eclk", "decon0_vclk".

- i80-if-timings: timing configuration for lcd i80 interface support.

Optional Properties:

- power-domains: a phandle to DECON power domain node.

- display-timings: timing settings for DECON, as described in document [1].

		Can be used in case timings cannot be provided otherwise

		or to override timings provided by the panel.

[1]: Documentation/devicetree/bindings/display/panel/display-timing.txt

Example:

SoC specific DT entry:

	decon@13930000 {

		compatible = "samsung,exynos7-decon";

		interrupt-parent = <&combiner>;

		reg = <0x13930000 0x1000>;

		interrupt-names = "lcd_sys", "vsync", "fifo";

		interrupts = <0 188 0>, <0 189 0>, <0 190 0>;

		clocks = <&clock_disp PCLK_DECON_INT>,

			 <&clock_disp ACLK_DECON_INT>,

			 <&clock_disp SCLK_DECON_INT_ECLK>,

			 <&clock_disp SCLK_DECON_INT_EXTCLKPLL>;

		clock-names = "pclk_decon0", "aclk_decon0", "decon0_eclk",

				"decon0_vclk";

		status = "disabled";

	};

Board specific DT entry:

	decon@13930000 {

		pinctrl-0 = <&lcd_clk &pwm1_out>;

		pinctrl-names = "default";

		status = "okay";

	};

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/display/samsung/samsung,exynos7-decon.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung Exynos7 SoC Display and Enhancement Controller (DECON)

maintainers:

  - Inki Dae <inki.dae@samsung.com>

  - Joonyoung Shim <jy0922.shim@samsung.com>

  - Seung-Woo Kim <sw0312.kim@samsung.com>

  - Kyungmin Park <kyungmin.park@samsung.com>

  - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>

description: |

  DECON (Display and Enhancement Controller) is the Display Controller for the

  Exynos7 series of SoCs which transfers the image data from a video memory

  buffer to an external LCD interface.

properties:

  compatible:

    const: samsung,exynos7-decon

  clocks:

    minItems: 4

    maxItems: 4

  clock-names:

    items:

      - const: pclk_decon0

      - const: aclk_decon0

      - const: decon0_eclk

      - const: decon0_vclk

  display-timings:

    $ref: ../panel/display-timings.yaml#

  i80-if-timings:

    type: object

    description: timing configuration for lcd i80 interface support

    properties:

      cs-setup:

        $ref: /schemas/types.yaml#/definitions/uint32

        description:

          Clock cycles for the active period of address signal is enabled until

          chip select is enabled.

        default: 0

      wr-active:

        $ref: /schemas/types.yaml#/definitions/uint32

        description:

          Clock cycles for the active period of CS is enabled.

        default: 1

      wr-hold:

        $ref: /schemas/types.yaml#/definitions/uint32

        description:

          Clock cycles for the active period of CS is disabled until write

          signal is disabled.

        default: 0

      wr-setup:

        $ref: /schemas/types.yaml#/definitions/uint32

        description:

          Clock cycles for the active period of CS signal is enabled until

          write signal is enabled.

        default: 0

  interrupts:

    items:

      - description: FIFO level

      - description: VSYNC

      - description: LCD system

  interrupt-names:

    items:

      - const: fifo

      - const: vsync

      - const: lcd_sys

  power-domains:

    maxItems: 1

  reg:

    maxItems: 1

required:

  - compatible

  - clocks

  - clock-names

  - interrupts

  - interrupt-names

  - reg

additionalProperties: false

examples:

  - |

    #include <dt-bindings/clock/exynos7-clk.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    display-controller@13930000 {

        compatible = "samsung,exynos7-decon";

        reg = <0x13930000 0x1000>;

        interrupt-names = "fifo", "vsync", "lcd_sys";

        interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;

        clocks = <&clock_disp 100>, /* PCLK_DECON_INT */

                 <&clock_disp 101>, /* ACLK_DECON_INT */

                 <&clock_disp 102>, /* SCLK_DECON_INT_ECLK */

                 <&clock_disp 103>; /* SCLK_DECON_INT_EXTCLKPLL */

        clock-names = "pclk_decon0",

                      "aclk_decon0",

                      "decon0_eclk",

                      "decon0_vclk";

        pinctrl-0 = <&lcd_clk &pwm1_out>;

        pinctrl-names = "default";

    };