Commit 5c6e3d5a authored by Yanfei Xu's avatar Yanfei Xu Committed by Dave Jiang
Browse files

cxl/pci: Remove duplicated implementation of waiting for memory_info_valid 



commit ce17ad0d ("cxl: Wait Memory_Info_Valid before access memory
related info") added another implementation, which is
cxl_dvsec_mem_range_valid(), of waiting for memory_info_valid without
realizing it duplicated wait_for_valid(). Remove wait_for_valid() and
retain cxl_dvsec_mem_range_valid() as the former is hardcoded to check
only the Memory_Info_Valid bit of DVSEC range 1, while the latter allows
for selection between DVSEC range 1 or 2 via parameter.

Suggested-by: default avatarDan Williams <dan.j.williams@intel.com>
Reviewed-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: default avatarYanfei Xu <yanfei.xu@intel.com>
Reviewed-by: default avatarAlison Schofield <alison.schofield@intel.com>
Link: https://patch.msgid.link/20240828084231.1378789-3-yanfei.xu@intel.com


Signed-off-by: default avatarDave Jiang <dave.jiang@intel.com>
parent 55e26869

drivers/cxl/core/pci.c

+5 −36
Original line number Diff line number Diff line
@@ -211,37 +211,6 @@ int cxl_await_media_ready(struct cxl_dev_state *cxlds) 
}

EXPORT_SYMBOL_NS_GPL(cxl_await_media_ready, CXL);



static int wait_for_valid(struct pci_dev *pdev, int d)

{

	u32 val;

	int rc;



	/*

	 * Memory_Info_Valid: When set, indicates that the CXL Range 1 Size high

	 * and Size Low registers are valid. Must be set within 1 second of

	 * deassertion of reset to CXL device. Likely it is already set by the

	 * time this runs, but otherwise give a 1.5 second timeout in case of

	 * clock skew.

	 */

	rc = pci_read_config_dword(pdev, d + CXL_DVSEC_RANGE_SIZE_LOW(0), &val);

	if (rc)

		return rc;



	if (val & CXL_DVSEC_MEM_INFO_VALID)

		return 0;



	msleep(1500);



	rc = pci_read_config_dword(pdev, d + CXL_DVSEC_RANGE_SIZE_LOW(0), &val);

	if (rc)

		return rc;



	if (val & CXL_DVSEC_MEM_INFO_VALID)

		return 0;



	return -ETIMEDOUT;

}



static int cxl_set_mem_enable(struct cxl_dev_state *cxlds, u16 val)

{

	struct pci_dev *pdev = to_pci_dev(cxlds->dev);
@@ -322,11 +291,13 @@ static int devm_cxl_enable_hdm(struct device *host, struct cxl_hdm *cxlhdm) 
	return devm_add_action_or_reset(host, disable_hdm, cxlhdm);

}



int cxl_dvsec_rr_decode(struct device *dev, int d,

int cxl_dvsec_rr_decode(struct device *dev, struct cxl_port *port,

			struct cxl_endpoint_dvsec_info *info)

{

	struct pci_dev *pdev = to_pci_dev(dev);

	struct cxl_dev_state *cxlds = pci_get_drvdata(pdev);

	int hdm_count, rc, i, ranges = 0;

	int d = cxlds->cxl_dvsec;

	u16 cap, ctrl;



	if (!d) {
@@ -353,11 +324,9 @@ int cxl_dvsec_rr_decode(struct device *dev, int d, 
	if (!hdm_count || hdm_count > 2)

		return -EINVAL;



	rc = wait_for_valid(pdev, d);

	if (rc) {

		dev_dbg(dev, "Failure awaiting MEM_INFO_VALID (%d)\n", rc);

	rc = cxl_dvsec_mem_range_valid(cxlds, 0);

	if (rc)

		return rc;

	}



	/*

	 * The current DVSEC values are moot if the memory capability is

drivers/cxl/cxl.h

+1 −1
Original line number Diff line number Diff line
@@ -811,7 +811,7 @@ struct cxl_hdm *devm_cxl_setup_hdm(struct cxl_port *port, 
int devm_cxl_enumerate_decoders(struct cxl_hdm *cxlhdm,

				struct cxl_endpoint_dvsec_info *info);

int devm_cxl_add_passthrough_decoder(struct cxl_port *port);

int cxl_dvsec_rr_decode(struct device *dev, int dvsec,

int cxl_dvsec_rr_decode(struct device *dev, struct cxl_port *port,

			struct cxl_endpoint_dvsec_info *info);



bool is_cxl_region(struct device *dev);

drivers/cxl/port.c

+1 −1
Original line number Diff line number Diff line
@@ -98,7 +98,7 @@ static int cxl_endpoint_port_probe(struct cxl_port *port) 
	struct cxl_port *root;

	int rc;



	rc = cxl_dvsec_rr_decode(cxlds->dev, cxlds->cxl_dvsec, &info);

	rc = cxl_dvsec_rr_decode(cxlds->dev, port, &info);

	if (rc < 0)

		return rc;

tools/testing/cxl/test/mock.c

+2 −2
Original line number Diff line number Diff line
@@ -228,7 +228,7 @@ int __wrap_cxl_hdm_decode_init(struct cxl_dev_state *cxlds, 
}

EXPORT_SYMBOL_NS_GPL(__wrap_cxl_hdm_decode_init, CXL);



int __wrap_cxl_dvsec_rr_decode(struct device *dev, int dvsec,

int __wrap_cxl_dvsec_rr_decode(struct device *dev, struct cxl_port *port,

			       struct cxl_endpoint_dvsec_info *info)

{

	int rc = 0, index;
@@ -237,7 +237,7 @@ int __wrap_cxl_dvsec_rr_decode(struct device *dev, int dvsec, 
	if (ops && ops->is_mock_dev(dev))

		rc = 0;

	else

		rc = cxl_dvsec_rr_decode(dev, dvsec, info);

		rc = cxl_dvsec_rr_decode(dev, port, info);

	put_cxl_mock_ops(index);



	return rc;