Commit 5c89ceda authored by Ruijing Dong's avatar Ruijing Dong Committed by Alex Deucher
Browse files

drm/amdgpu/vcn: using separate VCN1_AON_SOC offset 



VCN1_AON_SOC_ADDRESS_3_0 offset varies on different
VCN generations, the issue in vcn4.0.5 is caused by
a different VCN1_AON_SOC_ADDRESS_3_0 offset.

This patch does the following:

    1. use the same offset for other VCN generations.
    2. use the vcn4.0.5 special offset
    3. update vcn_4_0 and vcn_5_0

Acked-by: default avatarSaleemkhan Jamadar <saleemkhan.jamadar@amd.com>
Reviewed-by: default avatarLeo Liu <leo.liu@amd.com>
Signed-off-by: default avatarRuijing Dong <ruijing.dong@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent af7160c2

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

+0 −1
Original line number Diff line number Diff line
@@ -66,7 +66,6 @@ 
#define VCN_ENC_CMD_REG_WAIT		0x0000000c



#define VCN_AON_SOC_ADDRESS_2_0 	0x1f800

#define VCN1_AON_SOC_ADDRESS_3_0 	0x48000

#define VCN_VID_IP_ADDRESS_2_0		0x0

#define VCN_AON_IP_ADDRESS_2_0		0x30000

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

+1 −0
Original line number Diff line number Diff line
@@ -39,6 +39,7 @@ 


#define VCN_VID_SOC_ADDRESS_2_0					0x1fa00

#define VCN1_VID_SOC_ADDRESS_3_0				0x48200

#define VCN1_AON_SOC_ADDRESS_3_0				0x48000



#define mmUVD_CONTEXT_ID_INTERNAL_OFFSET			0x1fd

#define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET			0x503

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

+1 −0
Original line number Diff line number Diff line
@@ -39,6 +39,7 @@ 


#define VCN_VID_SOC_ADDRESS_2_0					0x1fa00

#define VCN1_VID_SOC_ADDRESS_3_0				0x48200

#define VCN1_AON_SOC_ADDRESS_3_0				0x48000



#define mmUVD_CONTEXT_ID_INTERNAL_OFFSET			0x27

#define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET			0x0f

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

+1 −0
Original line number Diff line number Diff line
@@ -40,6 +40,7 @@ 


#define VCN_VID_SOC_ADDRESS_2_0					0x1fa00

#define VCN1_VID_SOC_ADDRESS_3_0				0x48200

#define VCN1_AON_SOC_ADDRESS_3_0				0x48000



#define mmUVD_CONTEXT_ID_INTERNAL_OFFSET			0x27

#define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET			0x0f

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

+3 −1
Original line number Diff line number Diff line
@@ -46,6 +46,7 @@ 


#define VCN_VID_SOC_ADDRESS_2_0							0x1fb00

#define VCN1_VID_SOC_ADDRESS_3_0						0x48300

#define VCN1_AON_SOC_ADDRESS_3_0						0x48000



#define VCN_HARVEST_MMSCH								0
@@ -614,7 +615,8 @@ static void vcn_v4_0_mc_resume_dpg_mode(struct amdgpu_vcn_inst *vinst, 


	/* VCN global tiling registers */

	WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(

		VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);

			VCN, inst_idx, regUVD_GFX10_ADDR_CONFIG),

			adev->gfx.config.gb_addr_config, 0, indirect);

}



/**