Commit 5c8d08f3 authored by Dmitry Osipenko's avatar Dmitry Osipenko Committed by Thierry Reding
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dt-bindings: memory: tegra: Add hot resets definitions 



Add definitions for the Tegra20+ memory controller hot resets.

Signed-off-by: default avatarDmitry Osipenko <digetx@gmail.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 60cc43fc

include/dt-bindings/memory/tegra114-mc.h

+19 −0
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@@ -23,4 +23,23 @@ 
#define TEGRA_SWGROUP_EMUCIF	18

#define TEGRA_SWGROUP_TSEC	19



#define TEGRA114_MC_RESET_AFI		0

#define TEGRA114_MC_RESET_AVPC		1

#define TEGRA114_MC_RESET_DC		2

#define TEGRA114_MC_RESET_DCB		3

#define TEGRA114_MC_RESET_EPP		4

#define TEGRA114_MC_RESET_2D		5

#define TEGRA114_MC_RESET_HC		6

#define TEGRA114_MC_RESET_HDA		7

#define TEGRA114_MC_RESET_ISP		8

#define TEGRA114_MC_RESET_MPCORE	9

#define TEGRA114_MC_RESET_MPCORELP	10

#define TEGRA114_MC_RESET_MPE		11

#define TEGRA114_MC_RESET_3D		12

#define TEGRA114_MC_RESET_3D2		13

#define TEGRA114_MC_RESET_PPCS		14

#define TEGRA114_MC_RESET_SATA		15

#define TEGRA114_MC_RESET_VDE		16

#define TEGRA114_MC_RESET_VI		17



#endif

include/dt-bindings/memory/tegra124-mc.h

+25 −0
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@@ -29,4 +29,29 @@ 
#define TEGRA_SWGROUP_VIC	24

#define TEGRA_SWGROUP_VI	25



#define TEGRA124_MC_RESET_AFI		0

#define TEGRA124_MC_RESET_AVPC		1

#define TEGRA124_MC_RESET_DC		2

#define TEGRA124_MC_RESET_DCB		3

#define TEGRA124_MC_RESET_HC		4

#define TEGRA124_MC_RESET_HDA		5

#define TEGRA124_MC_RESET_ISP2		6

#define TEGRA124_MC_RESET_MPCORE	7

#define TEGRA124_MC_RESET_MPCORELP	8

#define TEGRA124_MC_RESET_MSENC		9

#define TEGRA124_MC_RESET_PPCS		10

#define TEGRA124_MC_RESET_SATA		11

#define TEGRA124_MC_RESET_VDE		12

#define TEGRA124_MC_RESET_VI		13

#define TEGRA124_MC_RESET_VIC		14

#define TEGRA124_MC_RESET_XUSB_HOST	15

#define TEGRA124_MC_RESET_XUSB_DEV	16

#define TEGRA124_MC_RESET_TSEC		17

#define TEGRA124_MC_RESET_SDMMC1	18

#define TEGRA124_MC_RESET_SDMMC2	19

#define TEGRA124_MC_RESET_SDMMC3	20

#define TEGRA124_MC_RESET_SDMMC4	21

#define TEGRA124_MC_RESET_ISP2B		22

#define TEGRA124_MC_RESET_GPU		23



#endif

include/dt-bindings/memory/tegra20-mc.h

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+21 −0
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/* SPDX-License-Identifier: GPL-2.0 */

#ifndef DT_BINDINGS_MEMORY_TEGRA20_MC_H

#define DT_BINDINGS_MEMORY_TEGRA20_MC_H



#define TEGRA20_MC_RESET_AVPC		0

#define TEGRA20_MC_RESET_DC		1

#define TEGRA20_MC_RESET_DCB		2

#define TEGRA20_MC_RESET_EPP		3

#define TEGRA20_MC_RESET_2D		4

#define TEGRA20_MC_RESET_HC		5

#define TEGRA20_MC_RESET_ISP		6

#define TEGRA20_MC_RESET_MPCORE		7

#define TEGRA20_MC_RESET_MPEA		8

#define TEGRA20_MC_RESET_MPEB		9

#define TEGRA20_MC_RESET_MPEC		10

#define TEGRA20_MC_RESET_3D		11

#define TEGRA20_MC_RESET_PPCS		12

#define TEGRA20_MC_RESET_VDE		13

#define TEGRA20_MC_RESET_VI		14



#endif

include/dt-bindings/memory/tegra210-mc.h

+31 −0
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@@ -34,4 +34,35 @@ 
#define TEGRA_SWGROUP_ETR	29

#define TEGRA_SWGROUP_TSECB	30



#define TEGRA210_MC_RESET_AFI		0

#define TEGRA210_MC_RESET_AVPC		1

#define TEGRA210_MC_RESET_DC		2

#define TEGRA210_MC_RESET_DCB		3

#define TEGRA210_MC_RESET_HC		4

#define TEGRA210_MC_RESET_HDA		5

#define TEGRA210_MC_RESET_ISP2		6

#define TEGRA210_MC_RESET_MPCORE	7

#define TEGRA210_MC_RESET_NVENC		8

#define TEGRA210_MC_RESET_PPCS		9

#define TEGRA210_MC_RESET_SATA		10

#define TEGRA210_MC_RESET_VI		11

#define TEGRA210_MC_RESET_VIC		12

#define TEGRA210_MC_RESET_XUSB_HOST	13

#define TEGRA210_MC_RESET_XUSB_DEV	14

#define TEGRA210_MC_RESET_A9AVP		15

#define TEGRA210_MC_RESET_TSEC		16

#define TEGRA210_MC_RESET_SDMMC1	17

#define TEGRA210_MC_RESET_SDMMC2	18

#define TEGRA210_MC_RESET_SDMMC3	19

#define TEGRA210_MC_RESET_SDMMC4	20

#define TEGRA210_MC_RESET_ISP2B		21

#define TEGRA210_MC_RESET_GPU		22

#define TEGRA210_MC_RESET_NVDEC		23

#define TEGRA210_MC_RESET_APE		24

#define TEGRA210_MC_RESET_SE		25

#define TEGRA210_MC_RESET_NVJPG		26

#define TEGRA210_MC_RESET_AXIAP		27

#define TEGRA210_MC_RESET_ETR		28

#define TEGRA210_MC_RESET_TSECB		29



#endif

include/dt-bindings/memory/tegra30-mc.h

+19 −0
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@@ -22,4 +22,23 @@ 
#define TEGRA_SWGROUP_MPCORE	17

#define TEGRA_SWGROUP_ISP	18



#define TEGRA30_MC_RESET_AFI		0

#define TEGRA30_MC_RESET_AVPC		1

#define TEGRA30_MC_RESET_DC		2

#define TEGRA30_MC_RESET_DCB		3

#define TEGRA30_MC_RESET_EPP		4

#define TEGRA30_MC_RESET_2D		5

#define TEGRA30_MC_RESET_HC		6

#define TEGRA30_MC_RESET_HDA		7

#define TEGRA30_MC_RESET_ISP		8

#define TEGRA30_MC_RESET_MPCORE		9

#define TEGRA30_MC_RESET_MPCORELP	10

#define TEGRA30_MC_RESET_MPE		11

#define TEGRA30_MC_RESET_3D		12

#define TEGRA30_MC_RESET_3D2		13

#define TEGRA30_MC_RESET_PPCS		14

#define TEGRA30_MC_RESET_SATA		15

#define TEGRA30_MC_RESET_VDE		16

#define TEGRA30_MC_RESET_VI		17



#endif