Commit 5c983737 authored by Neil Armstrong's avatar Neil Armstrong
Browse files

drm/meson: gate px_clk when setting rate 



Disable the px_clk when setting the rate to recover a fully
configured and correctly reset VCLK clock tree after the rate
is set.

Fixes: 77d9e1e6 ("drm/meson: add support for MIPI-DSI transceiver")
Reviewed-by: default avatarNicolas Belin <nbelin@baylibre.com>
Link: https://lore.kernel.org/r/20240403-amlogic-v6-4-upstream-dsi-ccf-vim3-v12-4-99ecdfdc87fc@linaro.org


Signed-off-by: default avatarNeil Armstrong <neil.armstrong@linaro.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20240403-amlogic-v6-4-upstream-dsi-ccf-vim3-v12-4-99ecdfdc87fc@linaro.org
parent 105aa4c6

drivers/gpu/drm/meson/meson_dw_mipi_dsi.c

+7 −0
Original line number Diff line number Diff line
@@ -95,6 +95,7 @@ static int dw_mipi_dsi_phy_init(void *priv_data) 
		return ret;

	}



	clk_disable_unprepare(mipi_dsi->px_clk);

	ret = clk_set_rate(mipi_dsi->px_clk, mipi_dsi->mode->clock * 1000);



	if (ret) {
@@ -103,6 +104,12 @@ static int dw_mipi_dsi_phy_init(void *priv_data) 
		return ret;

	}



	ret = clk_prepare_enable(mipi_dsi->px_clk);

	if (ret) {

		dev_err(mipi_dsi->dev, "Failed to enable DSI Pixel clock (ret %d)\n", ret);

		return ret;

	}



	switch (mipi_dsi->dsi_device->format) {

	case MIPI_DSI_FMT_RGB888:

		dpi_data_format = DPI_COLOR_24BIT;