Commit 5cee04a8 authored by Neil Armstrong's avatar Neil Armstrong Committed by Vinod Koul
Browse files

phy: qcom: qmp-pcie: register PHY AUX clock for SM8[456]50 4x2 PCIe PHY 



The PCIe Gen4x2 PHY found in the SM8[456]50 SoCs have a second clock,
enable this second clock by setting the proper 20MHz hardware rate in
the Gen4x2 SM8[456]50 aux_clock_rate config fields.

Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: default avatarNeil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240322-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v2-4-3ec0a966d52f@linaro.org


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 583ca9cc

drivers/phy/qualcomm/phy-qcom-qmp-pcie.c

+9 −0
Original line number Diff line number Diff line
@@ -3141,6 +3141,9 @@ static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = { 


	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,

	.phy_status		= PHYSTATUS_4_20,



	/* 20MHz PHY AUX Clock */

	.aux_clock_rate		= 20000000,

};



static const struct qmp_phy_cfg sm8550_qmp_gen3x2_pciephy_cfg = {
@@ -3198,6 +3201,9 @@ static const struct qmp_phy_cfg sm8550_qmp_gen4x2_pciephy_cfg = { 
	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,

	.phy_status		= PHYSTATUS_4_20,

	.has_nocsr_reset	= true,



	/* 20MHz PHY AUX Clock */

	.aux_clock_rate		= 20000000,

};



static const struct qmp_phy_cfg sm8650_qmp_gen4x2_pciephy_cfg = {
@@ -3228,6 +3234,9 @@ static const struct qmp_phy_cfg sm8650_qmp_gen4x2_pciephy_cfg = { 
	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,

	.phy_status		= PHYSTATUS_4_20,

	.has_nocsr_reset	= true,



	/* 20MHz PHY AUX Clock */

	.aux_clock_rate		= 20000000,

};



static const struct qmp_phy_cfg sa8775p_qmp_gen4x2_pciephy_cfg = {