Commit 5d08559c authored by Jesse Zhang's avatar Jesse Zhang Committed by Alex Deucher
Browse files

drm/amdgpu/gfx_v12_0: set gfx.rs64_enable from PFP header on GFX12 



gfx_v12_0_init_microcode() always loads RS64 CP ucode but never set
adev->gfx.rs64_enable, so it stayed false and code that branches on it
(e.g. MEC pipe reset) used the legacy CP_MEC_CNTL path incorrectly.

Match GFX11: derive RS64 mode from the PFP firmware header (v2.0) via
amdgpu_ucode_hdr_version(). Log at debug when RS64 is enabled.

Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarJesse Zhang <jesse.zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
(cherry picked from commit b03d53598b0d2048e8fa7303b8d0784768ec4fa6)
parent 6bbede02

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

+7 −0
Original line number Diff line number Diff line
@@ -602,6 +602,13 @@ static int gfx_v12_0_init_microcode(struct amdgpu_device *adev) 
				   "amdgpu/%s_pfp.bin", ucode_prefix);

	if (err)

		goto out;



	adev->gfx.rs64_enable = amdgpu_ucode_hdr_version(

				(union amdgpu_firmware_header *)

				adev->gfx.pfp_fw->data, 2, 0);

	if (adev->gfx.rs64_enable)

		dev_dbg(adev->dev, "CP RS64 enable\n");



	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP);

	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK);