Commit 5d1a5c4f authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files

Merge tag 'coresight-next-v6.15' of... 

Merge tag 'coresight-next-v6.15' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/coresight/linux

 into char-misc-next

Suzuki writes:

coresight: updates for Linux v6.15

CoreSight self-hosted tracing driver subsystem update for Linux v6.15.
The update includes:
 - CoreSight trace capture for Panic/Watchdog timeouts
 - Fixes to ETM4x driver to synchronize register reads as required by the TRM
 - Support for Qualcomm CoreSight TMC Control Unit driver
 - Conversion of device locks to raw_spinlock for components that are used
   by the Perf mode.
 - Miscellaneous fixes for the subsystem

Signed-off-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>

* tag 'coresight-next-v6.15' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/coresight/linux: (41 commits)
  Coresight: Fix a NULL vs IS_ERR() bug in probe
  coresight: configfs: Constify struct config_item_type
  coresight: docs: Remove target sink from examples
  coresight/ultrasoc: change smb_drv_data spinlock's type to raw_spinlock_t
  coresight-tmc: change tmc_drvdata spinlock's type to raw_spinlock_t
  coresight-replicator: change replicator_drvdata spinlock's type to raw_spinlock_t
  coresight-funnel: change funnel_drvdata spinlock's type to raw_spinlock_t
  coresight-etb10: change etb_drvdata spinlock's type to raw_spinlock_t
  coresight-cti: change cti_drvdata spinlock's type to raw_spinlock_t
  coresight: change coresight_trace_id_map's lock type to raw_spinlock_t
  coresight-etm4x: change etmv4_drvdata spinlock type to raw_spinlock_t
  coresight: change coresight_device lock type to raw_spinlock_t
  coresight: add verification process for coresight_etm_get_trace_id
  Coresight: Add Coresight TMC Control Unit driver
  dt-bindings: arm: Add Coresight TMC Control Unit hardware
  Coresight: Change functions to accept the coresight_path
  Coresight: Change to read the trace ID from coresight_path
  Coresight: Allocate trace ID after building the path
  Coresight: Introduce a new struct coresight_path
  Coresight: Use coresight_etm_get_trace_id() in traceid_show()
  ...
parents a24b18aa 5442d22d

Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm

+15 −0
Original line number Diff line number Diff line
@@ -257,3 +257,18 @@ Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_t 
Description:

		(RW) Set/Get the MSR(mux select register) for the CMB subunit

		TPDM.



What:		/sys/bus/coresight/devices/<tpdm-name>/mcmb_trig_lane

Date:		Feb 2025

KernelVersion	6.15

Contact:	Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>

Description:

		(RW) Set/Get which lane participates in the output pattern

		match cross trigger mechanism for the MCMB subunit TPDM.



What:		/sys/bus/coresight/devices/<tpdm-name>/mcmb_lanes_select

Date:		Feb 2025

KernelVersion	6.15

Contact:	Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>

Description:

		(RW) Set/Get the enablement of the individual lane.

Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml

+26 −0
Original line number Diff line number Diff line
@@ -101,6 +101,29 @@ properties: 
          and ETF configurations.

        $ref: /schemas/graph.yaml#/properties/port



  memory-region:

    items:

      - description: Reserved trace buffer memory for ETR and ETF sinks.

          For ETR, this reserved memory region is used for trace data capture.

          Same region is used for trace data retention as well after a panic

          or watchdog reset.

          This reserved memory region is used as trace buffer or used for trace

          data retention only if specifically selected by the user in sysfs

          interface.

          The default memory usage models for ETR in sysfs/perf modes are

          otherwise unaltered.



          For ETF, this reserved memory region is used by default for

          retention of trace data synced from internal SRAM after a panic

          or watchdog reset.

      - description: Reserved meta data memory. Used for ETR and ETF sinks

          for storing metadata.



  memory-region-names:

    items:

      - const: tracedata

      - const: metadata



required:

  - compatible

  - reg
@@ -115,6 +138,9 @@ examples: 
    etr@20070000 {

        compatible = "arm,coresight-tmc", "arm,primecell";

        reg = <0x20070000 0x1000>;

        memory-region = <&etr_trace_mem_reserved>,

                       <&etr_mdata_mem_reserved>;

        memory-region-names = "tracedata", "metadata";



        clocks = <&oscclk6a>;

        clock-names = "apb_pclk";

Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml

0 → 100644
+84 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/arm/qcom,coresight-ctcu.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: CoreSight TMC Control Unit



maintainers:

  - Yuanfang Zhang <quic_yuanfang@quicinc.com>

  - Mao Jinlong <quic_jinlmao@quicinc.com>

  - Jie Gan <quic_jiegan@quicinc.com>



description: |

  The Trace Memory Controller(TMC) is used for Embedded Trace Buffer(ETB),

  Embedded Trace FIFO(ETF) and Embedded Trace Router(ETR) configurations.

  The configuration mode (ETB, ETF, ETR) is discovered at boot time when

  the device is probed.



  The Coresight TMC Control unit controls various Coresight behaviors.

  It works as a helper device when connected to TMC ETR device.

  It is responsible for controlling the data filter function based on

  the source device's Trace ID for TMC ETR device. The trace data with

  that Trace id can get into ETR's buffer while other trace data gets

  ignored.



properties:

  compatible:

    enum:

      - qcom,sa8775p-ctcu



  reg:

    maxItems: 1



  clocks:

    maxItems: 1



  clock-names:

    items:

      - const: apb



  in-ports:

    $ref: /schemas/graph.yaml#/properties/ports



    patternProperties:

      '^port(@[0-1])?$':

        description: Input connections from CoreSight Trace bus

        $ref: /schemas/graph.yaml#/properties/port



required:

  - compatible

  - reg

  - in-ports



additionalProperties: false



examples:

  - |

    ctcu@1001000 {

        compatible = "qcom,sa8775p-ctcu";

        reg = <0x1001000 0x1000>;



        clocks = <&aoss_qmp>;

        clock-names = "apb";



        in-ports {

            #address-cells = <1>;

            #size-cells = <0>;



            port@0 {

                reg = <0>;

                ctcu_in_port0: endpoint {

                    remote-endpoint = <&etr0_out_port>;

                };

            };



            port@1 {

                reg = <1>;

                ctcu_in_port1: endpoint {

                    remote-endpoint = <&etr1_out_port>;

                };

            };

        };

    };

Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml

+1 −2
Original line number Diff line number Diff line
@@ -55,8 +55,7 @@ properties: 
      - const: arm,primecell



  reg:

    minItems: 1

    maxItems: 2

    maxItems: 1



  clocks:

    maxItems: 1

Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml

+1 −2
Original line number Diff line number Diff line
@@ -41,8 +41,7 @@ properties: 
      - const: arm,primecell



  reg:

    minItems: 1

    maxItems: 2

    maxItems: 1



  qcom,dsb-element-bits:

    description: