Commit 5d1bbfba authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915/dp: convert interfaces to struct intel_display

parent 8146b923
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+3 −3
Original line number Diff line number Diff line
@@ -8156,7 +8156,7 @@ void intel_setup_outputs(struct drm_i915_private *dev_priv)
		intel_lvds_init(dev_priv);
		intel_crt_init(display);

		dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
		dpd_is_edp = intel_dp_is_port_edp(display, PORT_D);

		if (ilk_has_edp_a(dev_priv))
			g4x_dp_init(dev_priv, DP_A, PORT_A);
@@ -8202,14 +8202,14 @@ void intel_setup_outputs(struct drm_i915_private *dev_priv)
		 * trust the port type the VBT declares as we've seen at least
		 * HDMI ports that the VBT claim are DP or eDP.
		 */
		has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
		has_edp = intel_dp_is_port_edp(display, PORT_B);
		has_port = intel_bios_is_port_present(display, PORT_B);
		if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port)
			has_edp &= g4x_dp_init(dev_priv, VLV_DP_B, PORT_B);
		if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
			g4x_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);

		has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
		has_edp = intel_dp_is_port_edp(display, PORT_C);
		has_port = intel_bios_is_port_present(display, PORT_C);
		if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port)
			has_edp &= g4x_dp_init(dev_priv, VLV_DP_C, PORT_C);
+3 −6
Original line number Diff line number Diff line
@@ -573,8 +573,6 @@ void intel_display_driver_register(struct intel_display *display)
/* part #1: call before irq uninstall */
void intel_display_driver_remove(struct intel_display *display)
{
	struct drm_i915_private *i915 = to_i915(display->drm);

	if (!HAS_DISPLAY(display))
		return;

@@ -587,7 +585,7 @@ void intel_display_driver_remove(struct intel_display *display)
	 * fbdev after it's finalized. MST will be destroyed later as part of
	 * drm_mode_config_cleanup()
	 */
	intel_dp_mst_suspend(i915);
	intel_dp_mst_suspend(display);
}

/* part #2: call after irq uninstall */
@@ -672,7 +670,6 @@ void intel_display_driver_unregister(struct intel_display *display)
 */
int intel_display_driver_suspend(struct intel_display *display)
{
	struct drm_i915_private *i915 = to_i915(display->drm);
	struct drm_atomic_state *state;
	int ret;

@@ -690,7 +687,7 @@ int intel_display_driver_suspend(struct intel_display *display)
	/* ensure all DPT VMAs have been unpinned for intel_dpt_suspend() */
	flush_workqueue(display->wq.cleanup);

	intel_dp_mst_suspend(i915);
	intel_dp_mst_suspend(display);

	return ret;
}
@@ -747,7 +744,7 @@ void intel_display_driver_resume(struct intel_display *display)
		return;

	/* MST sideband requires HPD interrupts enabled */
	intel_dp_mst_resume(i915);
	intel_dp_mst_resume(display);

	display->restore.modeset_state = NULL;
	if (state)
+12 −24
Original line number Diff line number Diff line
@@ -828,9 +828,8 @@ small_joiner_ram_size_bits(struct intel_display *display)
		return 6144 * 8;
}

u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 pipe_bpp)
u32 intel_dp_dsc_nearest_valid_bpp(struct intel_display *display, u32 bpp, u32 pipe_bpp)
{
	struct intel_display *display = &i915->display;
	u32 bits_per_pixel = bpp;
	int i;

@@ -937,7 +936,7 @@ u32 get_max_compressed_bpp_with_joiner(struct intel_display *display,
	return max_bpp;
}

u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
u16 intel_dp_dsc_get_max_compressed_bpp(struct intel_display *display,
					u32 link_clock, u32 lane_count,
					u32 mode_clock, u32 mode_hdisplay,
					int num_joined_pipes,
@@ -945,7 +944,6 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
					u32 pipe_bpp,
					u32 timeslots)
{
	struct intel_display *display = &i915->display;
	u32 bits_per_pixel, joiner_max_bpp;

	/*
@@ -990,7 +988,7 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
							    mode_hdisplay, num_joined_pipes);
	bits_per_pixel = min(bits_per_pixel, joiner_max_bpp);

	bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(i915, bits_per_pixel, pipe_bpp);
	bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(display, bits_per_pixel, pipe_bpp);

	return bits_per_pixel;
}
@@ -1470,7 +1468,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
								true);
		} else if (drm_dp_sink_supports_fec(connector->dp.fec_capability)) {
			dsc_max_compressed_bpp =
				intel_dp_dsc_get_max_compressed_bpp(dev_priv,
				intel_dp_dsc_get_max_compressed_bpp(display,
								    max_link_clock,
								    max_lanes,
								    target_clock,
@@ -1488,7 +1486,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
		dsc = dsc_max_compressed_bpp && dsc_slice_count;
	}

	if (intel_dp_joiner_needs_dsc(dev_priv, num_joined_pipes) && !dsc)
	if (intel_dp_joiner_needs_dsc(display, num_joined_pipes) && !dsc)
		return MODE_CLOCK_HIGH;

	if (mode_rate > max_rate && !dsc)
@@ -1501,18 +1499,14 @@ intel_dp_mode_valid(struct drm_connector *_connector,
	return intel_mode_valid_max_plane_size(dev_priv, mode, num_joined_pipes);
}

bool intel_dp_source_supports_tps3(struct drm_i915_private *i915)
bool intel_dp_source_supports_tps3(struct intel_display *display)
{
	struct intel_display *display = &i915->display;

	return DISPLAY_VER(display) >= 9 ||
		display->platform.broadwell || display->platform.haswell;
}

bool intel_dp_source_supports_tps4(struct drm_i915_private *i915)
bool intel_dp_source_supports_tps4(struct intel_display *display)
{
	struct intel_display *display = &i915->display;

	return DISPLAY_VER(display) >= 10;
}

@@ -2590,11 +2584,9 @@ int intel_dp_config_required_rate(const struct intel_crtc_state *crtc_state)
	return intel_dp_link_required(adjusted_mode->crtc_clock, bpp);
}

bool intel_dp_joiner_needs_dsc(struct drm_i915_private *i915,
bool intel_dp_joiner_needs_dsc(struct intel_display *display,
			       int num_joined_pipes)
{
	struct intel_display *display = &i915->display;

	/*
	 * Pipe joiner needs compression up to display 12 due to bandwidth
	 * limitation. DG2 onwards pipe joiner can be enabled without
@@ -2612,7 +2604,6 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
			     bool respect_downstream_limits)
{
	struct intel_display *display = to_intel_display(encoder);
	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
	struct intel_connector *connector =
		to_intel_connector(conn_state->connector);
@@ -2634,7 +2625,7 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
	if (num_joined_pipes > 1)
		pipe_config->joiner_pipes = GENMASK(crtc->pipe + num_joined_pipes - 1, crtc->pipe);

	joiner_needs_dsc = intel_dp_joiner_needs_dsc(i915, num_joined_pipes);
	joiner_needs_dsc = intel_dp_joiner_needs_dsc(display, num_joined_pipes);

	dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en ||
		     !intel_dp_compute_config_limits(intel_dp, pipe_config,
@@ -6231,9 +6222,8 @@ static bool _intel_dp_is_port_edp(struct intel_display *display,
	return devdata && intel_bios_encoder_supports_edp(devdata);
}

bool intel_dp_is_port_edp(struct drm_i915_private *i915, enum port port)
bool intel_dp_is_port_edp(struct intel_display *display, enum port port)
{
	struct intel_display *display = &i915->display;
	const struct intel_bios_encoder_data *devdata =
		intel_bios_encoder_data_lookup(display, port);

@@ -6633,9 +6623,8 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
	return false;
}

void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
void intel_dp_mst_suspend(struct intel_display *display)
{
	struct intel_display *display = &dev_priv->display;
	struct intel_encoder *encoder;

	if (!HAS_DISPLAY(display))
@@ -6657,9 +6646,8 @@ void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
	}
}

void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
void intel_dp_mst_resume(struct intel_display *display)
{
	struct intel_display *display = &dev_priv->display;
	struct intel_encoder *encoder;

	if (!HAS_DISPLAY(display))
+10 −10
Original line number Diff line number Diff line
@@ -12,14 +12,14 @@ enum intel_output_format;
enum pipe;
enum port;
struct drm_connector_state;
struct drm_dp_vsc_sdp;
struct drm_encoder;
struct drm_i915_private;
struct drm_modeset_acquire_ctx;
struct drm_dp_vsc_sdp;
struct intel_atomic_state;
struct intel_connector;
struct intel_crtc_state;
struct intel_digital_port;
struct intel_display;
struct intel_dp;
struct intel_encoder;

@@ -87,15 +87,15 @@ bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state);
bool intel_dp_has_dsc(const struct intel_connector *connector);
int intel_dp_link_symbol_size(int rate);
int intel_dp_link_symbol_clock(int rate);
bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
bool intel_dp_is_port_edp(struct intel_display *display, enum port port);
enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *dig_port,
				  bool long_hpd);
void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
			    const struct drm_connector_state *conn_state);
void intel_edp_backlight_off(const struct drm_connector_state *conn_state);
void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp);
void intel_dp_mst_suspend(struct drm_i915_private *dev_priv);
void intel_dp_mst_resume(struct drm_i915_private *dev_priv);
void intel_dp_mst_suspend(struct intel_display *display);
void intel_dp_mst_resume(struct intel_display *display);
int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port);
int intel_dp_max_link_rate(struct intel_dp *intel_dp);
int intel_dp_max_lane_count(struct intel_dp *intel_dp);
@@ -112,15 +112,15 @@ void intel_dp_reset_link_params(struct intel_dp *intel_dp);

void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
			   u8 *link_bw, u8 *rate_select);
bool intel_dp_source_supports_tps3(struct drm_i915_private *i915);
bool intel_dp_source_supports_tps4(struct drm_i915_private *i915);
bool intel_dp_source_supports_tps3(struct intel_display *display);
bool intel_dp_source_supports_tps4(struct intel_display *display);

int intel_dp_link_required(int pixel_clock, int bpp);
int intel_dp_effective_data_rate(int pixel_clock, int bpp_x16,
				 int bw_overhead);
int intel_dp_max_link_data_rate(struct intel_dp *intel_dp,
				int max_dprx_rate, int max_dprx_lanes);
bool intel_dp_joiner_needs_dsc(struct drm_i915_private *i915,
bool intel_dp_joiner_needs_dsc(struct intel_display *display,
			       int num_joined_pipes);
bool intel_dp_has_joiner(struct intel_dp *intel_dp);
bool intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
@@ -137,7 +137,7 @@ bool intel_digital_port_connected(struct intel_encoder *encoder);
bool intel_digital_port_connected_locked(struct intel_encoder *encoder);
int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector,
				 u8 dsc_max_bpc);
u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
u16 intel_dp_dsc_get_max_compressed_bpp(struct intel_display *display,
					u32 link_clock, u32 lane_count,
					u32 mode_clock, u32 mode_hdisplay,
					int num_joined_pipes,
@@ -173,7 +173,7 @@ bool intel_dp_supports_fec(struct intel_dp *intel_dp,
bool intel_dp_supports_dsc(const struct intel_connector *connector,
			   const struct intel_crtc_state *crtc_state);

u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 pipe_bpp);
u32 intel_dp_dsc_nearest_valid_bpp(struct intel_display *display, u32 bpp, u32 pipe_bpp);

void intel_ddi_update_pipe(struct intel_atomic_state *state,
			   struct intel_encoder *encoder,
+2 −3
Original line number Diff line number Diff line
@@ -959,7 +959,6 @@ static u32 intel_dp_training_pattern(struct intel_dp *intel_dp,
				     enum drm_dp_phy dp_phy)
{
	struct intel_display *display = to_intel_display(intel_dp);
	struct drm_i915_private *i915 = to_i915(display->drm);
	bool source_tps3, sink_tps3, source_tps4, sink_tps4;

	/* UHBR+ use separate 128b/132b TPS2 */
@@ -972,7 +971,7 @@ static u32 intel_dp_training_pattern(struct intel_dp *intel_dp,
	 * TPS4 as of Feb 2018 as per VESA eDP_v1.4b_E1 specification.
	 * LTTPRs must support TPS4.
	 */
	source_tps4 = intel_dp_source_supports_tps4(i915);
	source_tps4 = intel_dp_source_supports_tps4(display);
	sink_tps4 = dp_phy != DP_PHY_DPRX ||
		    drm_dp_tps4_supported(intel_dp->dpcd);
	if (source_tps4 && sink_tps4) {
@@ -990,7 +989,7 @@ static u32 intel_dp_training_pattern(struct intel_dp *intel_dp,
	 * TPS3 support is mandatory for downstream devices that
	 * support HBR2. However, not all sinks follow the spec.
	 */
	source_tps3 = intel_dp_source_supports_tps3(i915);
	source_tps3 = intel_dp_source_supports_tps3(display);
	sink_tps3 = dp_phy != DP_PHY_DPRX ||
		    drm_dp_tps3_supported(intel_dp->dpcd);
	if (source_tps3 && sink_tps3) {
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