Commit 5d667003 authored by Charan Pedumuru's avatar Charan Pedumuru Committed by Vinod Koul
Browse files

dt-bindings: dma: atmel: Convert to json schema 



Convert old text based binding to json schema.
Changes during conversion:
- Add the required properties `clock` and `clock-names`, which were
  missing in the original binding.
- Add a fallback for `microchip,sam9x7-dma` and `microchip,sam9x60-dma`
  as they are compatible with the dma IP core on `atmel,sama5d4-dma`.
- Update examples and include appropriate file directives to resolve
  errors identified by `dt_binding_check` and `dtbs_check`.

Signed-off-by: default avatarCharan Pedumuru <charan.pedumuru@microchip.com>
Acked-by: default avatarConor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20241205-xdma-v1-1-76a4a44670b5@microchip.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 54e09c8e

Documentation/devicetree/bindings/dma/atmel,sama5d4-dma.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/dma/atmel,sama5d4-dma.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Microchip AT91 Extensible Direct Memory Access Controller



maintainers:

  - Nicolas Ferre <nicolas.ferre@microchip.com>

  - Charan Pedumuru <charan.pedumuru@microchip.com>



description:

  The DMA Controller (XDMAC) is a AHB-protocol central direct memory access

  controller. It performs peripheral data transfer and memory move operations

  over one or two bus ports through the unidirectional communication

  channel. Each channel is fully programmable and provides both peripheral

  or memory-to-memory transfers. The channel features are configurable at

  implementation.



allOf:

  - $ref: dma-controller.yaml#



properties:

  compatible:

    oneOf:

      - enum:

          - atmel,sama5d4-dma

          - microchip,sama7g5-dma

      - items:

          - enum:

              - microchip,sam9x60-dma

              - microchip,sam9x7-dma

          - const: atmel,sama5d4-dma



  "#dma-cells":

    description: |

      Represents the number of integer cells in the `dmas` property of client

      devices. The single cell specifies the channel configuration register:

        - bit 13: SIF (Source Interface Identifier) for memory interface.

        - bit 14: DIF (Destination Interface Identifier) for peripheral interface.

        - bit 30-24: PERID (Peripheral Identifier).

    const: 1



  reg:

    maxItems: 1



  interrupts:

    maxItems: 1



  clocks:

    maxItems: 1



  clock-names:

    const: dma_clk



required:

  - compatible

  - reg

  - interrupts

  - clocks

  - clock-names

  - "#dma-cells"



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/at91.h>

    #include <dt-bindings/dma/at91.h>

    #include <dt-bindings/interrupt-controller/irq.h>

    dma-controller@f0008000 {

        compatible = "atmel,sama5d4-dma";

        reg = <0xf0008000 0x1000>;

        interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;

        #dma-cells = <1>;

        clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;

        clock-names = "dma_clk";

    };

Documentation/devicetree/bindings/dma/atmel-xdma.txt

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* Atmel Extensible Direct Memory Access Controller (XDMAC)



* XDMA Controller

Required properties:

- compatible: Should be "atmel,sama5d4-dma", "microchip,sam9x60-dma" or

  "microchip,sama7g5-dma" or

  "microchip,sam9x7-dma", "atmel,sama5d4-dma".

- reg: Should contain DMA registers location and length.

- interrupts: Should contain DMA interrupt.

- #dma-cells: Must be <1>, used to represent the number of integer cells in

the dmas property of client devices.

  - The 1st cell specifies the channel configuration register:

    - bit 13: SIF, source interface identifier, used to get the memory

    interface identifier,

    - bit 14: DIF, destination interface identifier, used to get the peripheral

    interface identifier,

    - bit 30-24: PERID, peripheral identifier.



Example:



dma1: dma-controller@f0004000 {

	compatible = "atmel,sama5d4-dma";

	reg = <0xf0004000 0x200>;

	interrupts = <50 4 0>;

	#dma-cells = <1>;

};





* DMA clients

DMA clients connected to the Atmel XDMA controller must use the format

described in the dma.txt file, using a one-cell specifier for each channel.

The two cells in order are:

1. A phandle pointing to the DMA controller.

2. Channel configuration register. Configurable fields are:

    - bit 13: SIF, source interface identifier, used to get the memory

    interface identifier,

    - bit 14: DIF, destination interface identifier, used to get the peripheral

    interface identifier,

  - bit 30-24: PERID, peripheral identifier.



Example:



i2c2: i2c@f8024000 {

	compatible = "atmel,at91sam9x5-i2c";

	reg = <0xf8024000 0x4000>;

	interrupts = <34 4 6>;

	dmas = <&dma1

		(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)

		 | AT91_XDMAC_DT_PERID(6))>,

	       <&dma1

		(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)

		| AT91_XDMAC_DT_PERID(7))>;

	dma-names = "tx", "rx";

};