Unverified Commit 5d6c4776 authored by Andy Shevchenko's avatar Andy Shevchenko Committed by Stephen Boyd
Browse files

clk: baikal-t1: Remove not-going-to-be-supported code for Baikal SoC 



As noticed in the discussion [1] the Baikal SoC and platforms
are not going to be finalized, hence remove stale code.

Reviewed-by: default avatarBrian Masney <bmasney@redhat.com>
Link: https://lore.kernel.org/lkml/22b92ddf-6321-41b5-8073-f9c7064d3432@infradead.org/

 [1]
Signed-off-by: default avatarAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: default avatarRob Herring (Arm) <robh@kernel.org>
Reviewed-by: default avatarRandy Dunlap <rdunlap@infradead.org>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 4d0f627a

Documentation/devicetree/bindings/clock/baikal,bt1-ccu-div.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-div.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Baikal-T1 Clock Control Unit Dividers



maintainers:

  - Serge Semin <fancer.lancer@gmail.com>



description: |

  Clocks Control Unit is the core of Baikal-T1 SoC System Controller

  responsible for the chip subsystems clocking and resetting. The CCU is

  connected with an external fixed rate oscillator, which signal is transformed

  into clocks of various frequencies and then propagated to either individual

  IP-blocks or to groups of blocks (clock domains). The transformation is done

  by means of an embedded into CCU PLLs and gateable/non-gateable dividers. The

  later ones are described in this binding. Each clock domain can be also

  individually reset by using the domain clocks divider configuration

  registers. Baikal-T1 CCU is logically divided into the next components:

  1) External oscillator (normally XTAL's 25 MHz crystal oscillator, but

     in general can provide any frequency supported by the CCU PLLs).

  2) PLLs clocks generators (PLLs).

  3) AXI-bus clock dividers (AXI) - described in this binding file.

  4) System devices reference clock dividers (SYS) - described in this binding

     file.

  which are connected with each other as shown on the next figure:



          +---------------+

          | Baikal-T1 CCU |

          |   +----+------|- MIPS P5600 cores

          | +-|PLLs|------|- DDR controller

          | | +----+      |

  +----+  | |  |  |       |

  |XTAL|--|-+  |  | +---+-|

  +----+  | |  |  +-|AXI|-|- AXI-bus

          | |  |    +---+-|

          | |  |          |

          | |  +----+---+-|- APB-bus

          | +-------|SYS|-|- Low-speed Devices

          |         +---+-|- High-speed Devices

          +---------------+



  Each sub-block is represented as a separate DT node and has an individual

  driver to be bound with.



  In order to create signals of wide range frequencies the external oscillator

  output is primarily connected to a set of CCU PLLs. Some of PLLs CLKOUT are

  then passed over CCU dividers to create signals required for the target clock

  domain (like AXI-bus or System Device consumers). The dividers have the

  following structure:



          +--------------+

  CLKIN --|->+----+ 1|\  |

  SETCLK--|--|/DIV|->| | |

  CLKDIV--|--|    |  | |-|->CLKLOUT

  LOCK----|--+----+  | | |

          |          |/  |

          |           |  |

  EN------|-----------+  |

  RST-----|--------------|->RSTOUT

          +--------------+



  where CLKIN is the reference clock coming either from CCU PLLs or from an

  external clock oscillator, SETCLK - a command to update the output clock in

  accordance with a set divider, CLKDIV - clocks divider, LOCK - a signal of

  the output clock stabilization, EN - enable/disable the divider block,

  RST/RSTOUT - reset clocks domain signal. Depending on the consumer IP-core

  peculiarities the dividers may lack of some functionality depicted on the

  figure above (like EN, CLKDIV/LOCK/SETCLK). In this case the corresponding

  clock provider just doesn't expose either switching functions, or the rate

  configuration, or both of them.



  The clock dividers, which output clock is then consumed by the SoC individual

  devices, are united into a single clocks provider called System Devices CCU.

  Similarly the dividers with output clocks utilized as AXI-bus reference clocks

  are called AXI-bus CCU. Both of them use the common clock bindings with no

  custom properties. The list of exported clocks and reset signals can be found

  in the files: 'include/dt-bindings/clock/bt1-ccu.h' and

  'include/dt-bindings/reset/bt1-ccu.h'. Since System Devices and AXI-bus CCU

  are a part of the Baikal-T1 SoC System Controller their DT nodes are supposed

  to be a children of later one.



if:

  properties:

    compatible:

      contains:

        const: baikal,bt1-ccu-axi



then:

  properties:

    clocks:

      items:

        - description: CCU SATA PLL output clock

        - description: CCU PCIe PLL output clock

        - description: CCU Ethernet PLL output clock



    clock-names:

      items:

        - const: sata_clk

        - const: pcie_clk

        - const: eth_clk



else:

  properties:

    clocks:

      items:

        - description: External reference clock

        - description: CCU SATA PLL output clock

        - description: CCU PCIe PLL output clock

        - description: CCU Ethernet PLL output clock



    clock-names:

      items:

        - const: ref_clk

        - const: sata_clk

        - const: pcie_clk

        - const: eth_clk



properties:

  compatible:

    enum:

      - baikal,bt1-ccu-axi

      - baikal,bt1-ccu-sys



  reg:

    maxItems: 1



  "#clock-cells":

    const: 1



  "#reset-cells":

    const: 1



  clocks:

    minItems: 3

    maxItems: 4



  clock-names:

    minItems: 3

    maxItems: 4



additionalProperties: false



required:

  - compatible

  - "#clock-cells"

  - clocks

  - clock-names



examples:

  # AXI-bus Clock Control Unit node:

  - |

    #include <dt-bindings/clock/bt1-ccu.h>



    clock-controller@1f04d030 {

      compatible = "baikal,bt1-ccu-axi";

      reg = <0x1f04d030 0x030>;

      #clock-cells = <1>;

      #reset-cells = <1>;



      clocks = <&ccu_pll CCU_SATA_PLL>,

               <&ccu_pll CCU_PCIE_PLL>,

               <&ccu_pll CCU_ETH_PLL>;

      clock-names = "sata_clk", "pcie_clk", "eth_clk";

    };

  # System Devices Clock Control Unit node:

  - |

    #include <dt-bindings/clock/bt1-ccu.h>



    clock-controller@1f04d060 {

      compatible = "baikal,bt1-ccu-sys";

      reg = <0x1f04d060 0x0a0>;

      #clock-cells = <1>;

      #reset-cells = <1>;



      clocks = <&clk25m>,

               <&ccu_pll CCU_SATA_PLL>,

               <&ccu_pll CCU_PCIE_PLL>,

               <&ccu_pll CCU_ETH_PLL>;

      clock-names = "ref_clk", "sata_clk", "pcie_clk",

                    "eth_clk";

    };

  # Required Clock Control Unit PLL node:

  - |

    ccu_pll: clock-controller@1f04d000 {

      compatible = "baikal,bt1-ccu-pll";

      reg = <0x1f04d000 0x028>;

      #clock-cells = <1>;



      clocks = <&clk25m>;

      clock-names = "ref_clk";

    };

...

Documentation/devicetree/bindings/clock/baikal,bt1-ccu-pll.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-pll.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Baikal-T1 Clock Control Unit PLL



maintainers:

  - Serge Semin <fancer.lancer@gmail.com>



description: |

  Clocks Control Unit is the core of Baikal-T1 SoC System Controller

  responsible for the chip subsystems clocking and resetting. The CCU is

  connected with an external fixed rate oscillator, which signal is transformed

  into clocks of various frequencies and then propagated to either individual

  IP-blocks or to groups of blocks (clock domains). The transformation is done

  by means of PLLs and gateable/non-gateable dividers embedded into the CCU.

  It's logically divided into the next components:

  1) External oscillator (normally XTAL's 25 MHz crystal oscillator, but

     in general can provide any frequency supported by the CCU PLLs).

  2) PLLs clocks generators (PLLs) - described in this binding file.

  3) AXI-bus clock dividers (AXI).

  4) System devices reference clock dividers (SYS).

  which are connected with each other as shown on the next figure:



          +---------------+

          | Baikal-T1 CCU |

          |   +----+------|- MIPS P5600 cores

          | +-|PLLs|------|- DDR controller

          | | +----+      |

  +----+  | |  |  |       |

  |XTAL|--|-+  |  | +---+-|

  +----+  | |  |  +-|AXI|-|- AXI-bus

          | |  |    +---+-|

          | |  |          |

          | |  +----+---+-|- APB-bus

          | +-------|SYS|-|- Low-speed Devices

          |         +---+-|- High-speed Devices

          +---------------+



  Each CCU sub-block is represented as a separate dts-node and has an

  individual driver to be bound with.



  In order to create signals of wide range frequencies the external oscillator

  output is primarily connected to a set of CCU PLLs. There are five PLLs

  to create a clock for the MIPS P5600 cores, the embedded DDR controller,

  SATA, Ethernet and PCIe domains. The last three domains though named by the

  biggest system interfaces in fact include nearly all of the rest SoC

  peripherals. Each of the PLLs is based on True Circuits TSMC CLN28HPM core

  with an interface wrapper (so called safe PLL' clocks switcher) to simplify

  the PLL configuration procedure. The PLLs work as depicted on the next

  diagram:



      +--------------------------+

      |                          |

      +-->+---+    +---+   +---+ |  +---+   0|\

  CLKF--->|/NF|--->|PFD|...|VCO|-+->|/OD|--->| |

          +---+ +->+---+   +---+ /->+---+    | |--->CLKOUT

  CLKOD---------C----------------+          1| |

       +--------C--------------------------->|/

       |        |                             ^

  Rclk-+->+---+ |                             |

  CLKR--->|/NR|-+                             |

          +---+                               |

  BYPASS--------------------------------------+

  BWADJ--->



  where Rclk is the reference clock coming  from XTAL, NR - reference clock

  divider, NF - PLL clock multiplier, OD - VCO output clock divider, CLKOUT -

  output clock, BWADJ is the PLL bandwidth adjustment parameter. At this moment

  the binding supports the PLL dividers configuration in accordance with a

  requested rate, while bypassing and bandwidth adjustment settings can be

  added in future if it gets to be necessary.



  The PLLs CLKOUT is then either directly connected with the corresponding

  clocks consumer (like P5600 cores or DDR controller) or passed over a CCU

  divider to create a signal required for the clock domain.



  The CCU PLL dts-node uses the common clock bindings with no custom

  parameters. The list of exported clocks can be found in

  'include/dt-bindings/clock/bt1-ccu.h'. Since CCU PLL is a part of the

  Baikal-T1 SoC System Controller its DT node is supposed to be a child of

  later one.



properties:

  compatible:

    const: baikal,bt1-ccu-pll



  reg:

    maxItems: 1



  "#clock-cells":

    const: 1



  clocks:

    description: External reference clock

    maxItems: 1



  clock-names:

    const: ref_clk



additionalProperties: false



required:

  - compatible

  - "#clock-cells"

  - clocks

  - clock-names



examples:

  # Clock Control Unit PLL node:

  - |

    clock-controller@1f04d000 {

      compatible = "baikal,bt1-ccu-pll";

      reg = <0x1f04d000 0x028>;

      #clock-cells = <1>;



      clocks = <&clk25m>;

      clock-names = "ref_clk";

    };

  # Required external oscillator:

  - |

    clk25m: clock-oscillator-25m {

      compatible = "fixed-clock";

      #clock-cells = <0>;

      clock-frequency = <25000000>;

      clock-output-names = "clk25m";

    };

...

drivers/clk/Kconfig

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@@ -502,7 +502,6 @@ config COMMON_CLK_RPMI 
source "drivers/clk/actions/Kconfig"

source "drivers/clk/analogbits/Kconfig"

source "drivers/clk/aspeed/Kconfig"

source "drivers/clk/baikal-t1/Kconfig"

source "drivers/clk/bcm/Kconfig"

source "drivers/clk/hisilicon/Kconfig"

source "drivers/clk/imgtec/Kconfig"

drivers/clk/Makefile

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@@ -116,7 +116,6 @@ obj-y += aspeed/ 
obj-$(CONFIG_COMMON_CLK_AT91)		+= at91/

obj-$(CONFIG_ARCH_ARTPEC)		+= axis/

obj-$(CONFIG_ARC_PLAT_AXS10X)		+= axs10x/

obj-$(CONFIG_CLK_BAIKAL_T1)		+= baikal-t1/

obj-y					+= bcm/

obj-$(CONFIG_ARCH_BERLIN)		+= berlin/

obj-$(CONFIG_ARCH_DAVINCI)		+= davinci/

drivers/clk/baikal-t1/Kconfig

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# SPDX-License-Identifier: GPL-2.0-only

config CLK_BAIKAL_T1

	bool "Baikal-T1 Clocks Control Unit interface"

	depends on (MIPS_BAIKAL_T1 && OF) || COMPILE_TEST

	default MIPS_BAIKAL_T1

	help

	  Clocks Control Unit is the core of Baikal-T1 SoC System Controller

	  responsible for the chip subsystems clocking and resetting. It

	  consists of multiple global clock domains, which can be reset by

	  means of the CCU control registers. These domains and devices placed

	  in them are fed with clocks generated by a hierarchy of PLLs,

	  configurable and fixed clock dividers. Enable this option to be able

	  to select Baikal-T1 CCU PLLs and Dividers drivers.



if CLK_BAIKAL_T1



config CLK_BT1_CCU_PLL

	bool "Baikal-T1 CCU PLLs support"

	select MFD_SYSCON

	default MIPS_BAIKAL_T1

	help

	  Enable this to support the PLLs embedded into the Baikal-T1 SoC

	  System Controller. These are five PLLs placed at the root of the

	  clocks hierarchy, right after an external reference oscillator

	  (normally of 25MHz). They are used to generate high frequency

	  signals, which are either directly wired to the consumers (like

	  CPUs, DDR, etc.) or passed over the clock dividers to be only

	  then used as an individual reference clock of a target device.



config CLK_BT1_CCU_DIV

	bool "Baikal-T1 CCU Dividers support"

	select MFD_SYSCON

	default MIPS_BAIKAL_T1

	help

	  Enable this to support the CCU dividers used to distribute clocks

	  between AXI-bus and system devices coming from CCU PLLs of Baikal-T1

	  SoC. CCU dividers can be either configurable or with fixed divider,

	  either gateable or ungateable. Some of the CCU dividers can be as well

	  used to reset the domains they're supplying clock to.



config CLK_BT1_CCU_RST

	bool "Baikal-T1 CCU Resets support"

	select RESET_CONTROLLER

	select MFD_SYSCON

	default MIPS_BAIKAL_T1

	help

	  Enable this to support the CCU reset blocks responsible for the

	  AXI-bus and some subsystems reset. These are mainly the

	  self-deasserted reset controls but there are several lines which

	  can be directly asserted/de-asserted (PCIe and DDR sub-domains).



endif