Unverified Commit 5daa3726 authored Dec 12, 2023 by Frederik Haxel Committed by Palmer Dabbelt Jan 09, 2024

riscv: Fixed wrong register in XIP_FIXUP_FLASH_OFFSET macro



During the refactoring, a bug was introduced in the rarly used
XIP_FIXUP_FLASH_OFFSET macro.

Fixes: bee7fbc3 ("RISC-V CPU Idle Support")
Fixes: e7681beb ("RISC-V: Split out the XIP fixups into their own file")

Signed-off-by: Frederik Haxel <haxel@fzi.de>
Link: https://lore.kernel.org/r/20231212130116.848530-3-haxel@fzi.de


Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

parent 66f1e680

arch/riscv/include/asm/xip_fixup.h

+1 −1

Original line number	Diff line number	Diff line
		@@ -13,7 +13,7 @@
		add \reg, \reg, t0
		.endm
		.macro XIP_FIXUP_FLASH_OFFSET reg
		la t1, __data_loc
		la t0, __data_loc
		REG_L t1, _xip_phys_offset
		sub \reg, \reg, t1
		add \reg, \reg, t0