Commit 5db5025d authored by Biju Das's avatar Biju Das Committed by Greg Kroah-Hartman
Browse files

usb: host: xhci-rcar: Add Renesas RZ/G3E USB3 Host driver support



The USB3.2 Gen2 Host controller (a.k.a USB3HOST), IP found on the RZ/G3E
SoC is similar to R-Car XHCI, but it doesn't require any firmware.

Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20250916150255.4231-7-biju.das.jz@bp.renesas.com


Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 2ef16e4e
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+1 −1
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@@ -93,7 +93,7 @@ config USB_XHCI_RCAR
	default ARCH_RENESAS
	help
	  Say 'Y' to enable the support for the xHCI host controller
	  found in Renesas R-Car ARM SoCs.
	  found in Renesas R-Car and RZ/G3E alike ARM SoCs.

config USB_XHCI_RZV2M
	bool "xHCI support for Renesas RZ/V2M SoC"
+55 −0
Original line number Diff line number Diff line
@@ -11,10 +11,12 @@
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/usb/phy.h>
#include <linux/reset.h>

#include "xhci.h"
#include "xhci-plat.h"
#include "xhci-rcar-regs.h"
#include "xhci-rzg3e-regs.h"
#include "xhci-rzv2m.h"

#define XHCI_RCAR_FIRMWARE_NAME_V1	"r8a779x_usb3_v1.dlmem"
@@ -67,6 +69,48 @@ static void xhci_rcar_start(struct usb_hcd *hcd)
	}
}

static void xhci_rzg3e_start(struct usb_hcd *hcd)
{
	u32 int_en;

	if (hcd->regs) {
		/* Update the controller initial setting */
		writel(0x03130200, hcd->regs + RZG3E_USB3_HOST_U3P0PIPESC(0));
		writel(0x00160200, hcd->regs + RZG3E_USB3_HOST_U3P0PIPESC(1));
		writel(0x03150000, hcd->regs + RZG3E_USB3_HOST_U3P0PIPESC(2));
		writel(0x03130200, hcd->regs + RZG3E_USB3_HOST_U3P0PIPESC(3));
		writel(0x00180000, hcd->regs + RZG3E_USB3_HOST_U3P0PIPESC(4));

		/* Interrupt Enable */
		int_en = readl(hcd->regs + RZG3E_USB3_HOST_INTEN);
		int_en |= RZG3E_USB3_HOST_INTEN_ENA;
		writel(int_en, hcd->regs + RZG3E_USB3_HOST_INTEN);
	}
}

static int xhci_rzg3e_resume(struct usb_hcd *hcd)
{
	struct xhci_hcd *xhci = hcd_to_xhci(hcd);

	return reset_control_deassert(xhci->reset);
}

static int xhci_rzg3e_post_resume(struct usb_hcd *hcd)
{
	xhci_rzg3e_start(hcd);

	return 0;
}

static int xhci_rzg3e_suspend(struct usb_hcd *hcd)
{
	struct xhci_hcd *xhci = hcd_to_xhci(hcd);

	reset_control_assert(xhci->reset);

	return 0;
}

static int xhci_rcar_download_firmware(struct usb_hcd *hcd)
{
	struct device *dev = hcd->self.controller;
@@ -190,6 +234,14 @@ static const struct xhci_plat_priv xhci_plat_renesas_rzv2m = {
	.plat_start = xhci_rzv2m_start,
};

static const struct xhci_plat_priv xhci_plat_renesas_rzg3e = {
	.quirks = XHCI_NO_64BIT_SUPPORT | XHCI_RESET_ON_RESUME | XHCI_SUSPEND_RESUME_CLKS,
	.plat_start = xhci_rzg3e_start,
	.suspend_quirk = xhci_rzg3e_suspend,
	.resume_quirk = xhci_rzg3e_resume,
	.post_resume_quirk = xhci_rzg3e_post_resume,
};

static const struct of_device_id usb_xhci_of_match[] = {
	{
		.compatible = "renesas,xhci-r8a7790",
@@ -206,6 +258,9 @@ static const struct of_device_id usb_xhci_of_match[] = {
	}, {
		.compatible = "renesas,xhci-r8a7796",
		.data = &xhci_plat_renesas_rcar_gen3,
	}, {
		.compatible = "renesas,r9a09g047-xhci",
		.data = &xhci_plat_renesas_rzg3e,
	}, {
		.compatible = "renesas,rcar-gen2-xhci",
		.data = &xhci_plat_renesas_rcar_gen2,
+12 −0
Original line number Diff line number Diff line
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __XHCI_RZG3E_H
#define __XHCI_RZG3E_H

#define RZG3E_USB3_HOST_INTEN		0x1044	/* Interrupt Enable */
#define RZG3E_USB3_HOST_U3P0PIPESC(x)	(0x10c0 + (x) * 4) /* PIPE Status and Control Register */

#define RZG3E_USB3_HOST_INTEN_XHC	BIT(0)
#define RZG3E_USB3_HOST_INTEN_HSE	BIT(2)
#define RZG3E_USB3_HOST_INTEN_ENA	(RZG3E_USB3_HOST_INTEN_XHC | RZG3E_USB3_HOST_INTEN_HSE)

#endif /* __XHCI_RZG3E_H */