Commit 5e25f996 authored by Ankit Nautiyal's avatar Ankit Nautiyal
Browse files

drm/i915/dp_mst: Use VRR Timing generator for DP MST for fixed_rr



Currently the variable timings are supported only for DP and eDP and not
for DP MST. Call intel_vrr_compute_config() for MST which will configure
fixed refresh rate timings irrespective of whether VRR is supported or
not. Since vrr_capable still doesn't have support for DP MST this will be
just treated as non VRR case and vrr.vmin/vmax/flipline will be all set
to adjusted_mode->crtc_vtotal.

This will help to move away from the legacy timing generator and
always use VRR timing generator by default.

With this change, we need to exclude MST in intel_vrr_is_capable for
now, to avoid having LRR with MST.

v2: Exclude MST in intel_vrr_is_capable() for now. (Ville)

Signed-off-by: default avatarAnkit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://lore.kernel.org/r/20250324133248.4071909-3-ankit.k.nautiyal@intel.com
parent 635125e3
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+3 −0
Original line number Diff line number Diff line
@@ -52,6 +52,7 @@
#include "intel_pfit.h"
#include "intel_psr.h"
#include "intel_vdsc.h"
#include "intel_vrr.h"
#include "skl_scaler.h"

/*
@@ -710,6 +711,8 @@ static int mst_stream_compute_config(struct intel_encoder *encoder,
		pipe_config->lane_lat_optim_mask =
			bxt_dpio_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);

	intel_vrr_compute_config(pipe_config, conn_state);

	intel_dp_audio_compute_config(encoder, pipe_config, conn_state);

	intel_ddi_compute_min_voltage_level(pipe_config);
+2 −0
Original line number Diff line number Diff line
@@ -32,6 +32,8 @@ bool intel_vrr_is_capable(struct intel_connector *connector)
			return false;
		fallthrough;
	case DRM_MODE_CONNECTOR_DisplayPort:
		if (connector->mst.dp)
			return false;
		intel_dp = intel_attached_dp(connector);

		if (!drm_dp_sink_can_do_video_without_timing_msa(intel_dp->dpcd))