Commit 5e30c16b authored by Kevin Brodsky's avatar Kevin Brodsky Committed by Catalin Marinas
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Documentation: arm64: Update memory.rst for TBI 



Most of memory.rst was written very early, at a time where TBI (Top
Byte Ignore) was not enabled. Nowadays TBI0 is always enabled, and
TBI1 may be enabled, depending on the kernel configuration. This
means that VA bits 63:56 cannot generally be assumed to have any
particular value.

Regardless of TBI, TTBRx selection is done based on bit 55; update
memory.rst accordingly.

Signed-off-by: default avatarKevin Brodsky <kevin.brodsky@arm.com>
Acked-by: default avatarMark Rutland <mark.rutland@arm.com>
Link: https://lore.kernel.org/r/20240702091349.356008-1-kevin.brodsky@arm.com


Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent 83a7eefe

Documentation/arch/arm64/memory.rst

+20 −22
Original line number Diff line number Diff line
@@ -18,12 +18,10 @@ ARMv8.2 adds optional support for Large Virtual Address space. This is 
only available when running with a 64KB page size and expands the

number of descriptors in the first level of translation.



User addresses have bits 63:48 set to 0 while the kernel addresses have

the same bits set to 1. TTBRx selection is given by bit 63 of the

virtual address. The swapper_pg_dir contains only kernel (global)

mappings while the user pgd contains only user (non-global) mappings.

The swapper_pg_dir address is written to TTBR1 and never written to

TTBR0.

TTBRx selection is given by bit 55 of the virtual address. The

swapper_pg_dir contains only kernel (global) mappings while the user pgd

contains only user (non-global) mappings.  The swapper_pg_dir address is

written to TTBR1 and never written to TTBR0.





AArch64 Linux memory layout with 4KB pages + 4 levels (48-bit)::
@@ -72,7 +70,7 @@ Translation table lookup with 4KB pages:: 
            |        |         |         +-----------> [29:21] L2 index

            |        |         +---------------------> [38:30] L1 index

            |        +-------------------------------> [47:39] L0 index

   +-------------------------------------------------> [63] TTBR0/1

            +----------------------------------------> [55] TTBR0/1





Translation table lookup with 64KB pages::
@@ -87,7 +85,7 @@ Translation table lookup with 64KB pages:: 
            |        |    +--------------------------> [41:29] L2 index

            |        +-------------------------------> [47:42] L1 index (48-bit)

            |                                          [51:42] L1 index (52-bit)

   +-------------------------------------------------> [63] TTBR0/1

            +----------------------------------------> [55] TTBR0/1





When using KVM without the Virtualization Host Extensions, the