Commit 5e3486e6 authored by Luke Wang's avatar Luke Wang Committed by Ulf Hansson
Browse files

mmc: sdhci: fix timing selection for 1-bit bus width 



When 1-bit bus width is used with HS200/HS400 capabilities set,
mmc_select_hs200() returns 0 without actually switching. This
causes mmc_select_timing() to skip mmc_select_hs(), leaving eMMC
in legacy mode (26MHz) instead of High Speed SDR (52MHz).

Per JEDEC eMMC spec section 5.3.2, 1-bit mode supports High Speed
SDR. Drop incompatible HS200/HS400/UHS/DDR caps early so timing
selection falls through to mmc_select_hs() correctly.

Fixes: f2119df6 ("mmc: sd: add support for signal voltage switch procedure")
Signed-off-by: default avatarLuke Wang <ziniu.wang_1@nxp.com>
Acked-by: default avatarAdrian Hunter <adrian.hunter@intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parent 2b76e0cc

drivers/mmc/host/sdhci.c

+8 −1
Original line number Diff line number Diff line
@@ -4532,8 +4532,15 @@ int sdhci_setup_host(struct sdhci_host *host) 
	 * their platform code before calling sdhci_add_host(), and we

	 * won't assume 8-bit width for hosts without that CAP.

	 */

	if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))

	if (host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA) {

		host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50);

		if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400)

			host->caps1 &= ~SDHCI_SUPPORT_HS400;

		mmc->caps2 &= ~(MMC_CAP2_HS200 | MMC_CAP2_HS400 | MMC_CAP2_HS400_ES);

		mmc->caps &= ~(MMC_CAP_DDR | MMC_CAP_UHS);

	} else {

		mmc->caps |= MMC_CAP_4_BIT_DATA;

	}



	if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)

		mmc->caps &= ~MMC_CAP_CMD23;